Hold time violation on clock falling edge with no clock falling edge used in RTL code

[alexpanrui]

Hi,
I was running post layout simulation in NCVerilog with lots of hold time violations on clock falling edge. The thing is that in my RTL design, i didn't use the clock falling edge to detect or trigger any signals. Can anyone explain to me why I am having the hold time violation on clock falling edge in post layout simulation? Thank you .

 

[rca]

is the violation are related to path connected to port or more generally to asynchronous signal?

 

[alexpanrui]

is the violation are related to path connected to port or more generally to asynchronous signal?

It is related to an asynchronous input.

 

[rca]

as the timing of the asynchronous input is unknown (versus the clock system), you should ignore or indicate to Mentor to ignore the timing check of these flops.
I could found tomorrow the command to ignore the timing check if you don't found.

 

[alexpanrui]

as the timing of the asynchronous input is unknown (versus the clock system), you should ignore or indicate to Mentor to ignore the timing check of these flops.
I could found tomorrow the command to ignore the timing check if you don't found.

So what you mean is that as the timing of the asynchronous input is unknown versus the clock system, simulator will have to check the timing of this input against both the rising and falling edge of the clock. Am I right? And please bear with me, why is Mentor involved here? I used DC for synthesis, SoC Encounter for P&R and NCVerilog for simulation. Thank you so much for your help

 

[rca]

ok sorry for Mentor remarq, you need to indicate to NCVerilog to no check the hold time on flop driven by an asynchronous signal, as this one is not related to the clock system.