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hold time and set up time

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anantha_09

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Which is more significant in final silicon? hold violation or setup
violation?

wat are the ways to overcome these two
 

pratap_v

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Hi,
Hold is more important bcoz if there is any setup voilatin one can avoid it by decreasing the frequency of operation. since hold is independent of frequency of operatiin u need to resolve the problem before implimenting the design on the silicon.
 

lakshman.ar

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After ur chip has come back from FAB and if u find

1) hold violation : its a dead chip, u cannot make it work wat so ever !!!

2) setup violation : reduce the frequency of the design and still u can make utr chip wrk !!

more significant violation to be looked at is ur "hold violation" .. evn if u r not meetin ur setup, u can make the chip wrk .. but hold ... u have to fix hold b4 design signoff !!!
 

mujju433

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How can u reduce the frequency to fix setup???????????????
 

vjm16

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Tsetup >= Tmax - (tcomb + tdff)

In the above equation, since tcomb and tdff cannot be changed after the chip is out, we can reduce the maximun frequency that the chip can work and thus meet the setup time violation.
 

sekapr

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final silicon should not have any violations either setup or hold
 

xinsu

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I think this should take your margin into account,maybe different margins for setup/hold,then the risk is different.
 

firewire2035

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mujju433 said:
How can u reduce the frequency to fix setup???????????????

Just slow the clock until all setup time requirement are met.
 

lakshman.ar

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@sekapr

"final silicon should not have any violations either setup or hold" ...

Well this depends, .... if u cannot afford a respin, then u can still make the chip wrk by reducing the clock speed at which the design works ( only if u have setup viol) !!

but ur ultimate goal b4 sign-off must be tht u have a positive slack for both setup and hold !!

WBR
Lakshman
 

renee_xu

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hi guys, I have question about the setup and hold time timing closure. I agree that hold time is important since it is independant of frequence. But what is the most significant aspect that will impact the hold time? I think the real silicon have a lot of noise and delay that will impact the minimum clock period. Is it also true for hold time?
 

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