OK, here are some simulation results:
* PLL 2nd order, VCO nominal frequency 50 kHz
* dc loop gain 1E6
* pole frequency 1.25 kHz, loop damping 0.64
* pull-in range: 15.3 kHz
* lock-in range: 3.3 kHz
* pull-out range: 3.5 kHz
* hold range: app. 200 kHz (theoretical value, in practice limited by VCO tuning range).
If I'm not mistaken, (a) is lock-in range(lock-in process) right?
Not exactly.
The lock-in range applies if the PLL is out of lock and can aquire lock within one beat cycle.
The pull-out range starts from a PLL that has locked (as in case (a)) and can remain in this stage in spite of a frequency step.
But both ranges don't differ very much.
Hi Lvw..I have one more question..How can we measure natural frequency wn from the simulation??
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My question is...how can I measure the center frequency of VCO (simulation)? Is it true that the input voltage of VCO should be zero to find the center frequency of the VCO?
Other than specification, there is no other way to check this?
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