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# [SOLVED]Hold range and Pull out range

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#### capital_zach

##### Junior Member level 3
Hi everyone,
I have a problem in understanding the difference between hold range and pull out range. It seems that this two are just the same. Can anybody help me to explain this?

From Roland E. Best:
The hold range: This is the frequency range in which a PLL can statically maintain phase tracking. A PLL is conditionally stable only within this range.

The pull-out range: This is the dynamic limit for stable operation of a PLL. If tracking is lost within this range, a PLL normally will lock again but this process can be slow if it is a pull-in process.

According to my knowledge the pull-out range is defined as the maximum frequency step that can be applied to the PLL input without loosing lock.
That means the only difference between pull-out and hold range is that the hold range is defined for a very slow sweep of the input frequency (static behaviour).

can you give me an example(if possible with value of pull-out range, input freq.)? I think I got the general idea but I want to know it better.

OK, here are some simulation results:
* PLL 2nd order, VCO nominal frequency 50 kHz
* dc loop gain 1E6
* pole frequency 1.25 kHz, loop damping 0.64
* pull-in range: 15.3 kHz
* lock-in range: 3.3 kHz
* pull-out range: 3.5 kHz
* hold range: app. 200 kHz (theoretical value, in practice limited by VCO tuning range).

OK, here are some simulation results:
* PLL 2nd order, VCO nominal frequency 50 kHz
* dc loop gain 1E6
* pole frequency 1.25 kHz, loop damping 0.64
* pull-in range: 15.3 kHz
* lock-in range: 3.3 kHz
* pull-out range: 3.5 kHz
* hold range: app. 200 kHz (theoretical value, in practice limited by VCO tuning range).

so for this simulation, if the initial input frequency is 50kHz and suddenly the input frequecy is change 54kHz(more than pull-out range), the PLL will locked out right? And this is called pull-out range.

And for hold range. If the initial input frequency is 50 kHz and the input frequency is increase step by step lower than pull-out range, the PLL will not be locked out until 250kHz.

Is my understanding right?

so for this simulation, if the initial input frequency is 50kHz and suddenly the input frequecy is change 54kHz(more than pull-out range), the PLL will locked out right? And this is called pull-out range.

Yes, but the pll is able to lock-in again because of the larger pull-in range.
The pull-out range is the range that defines the outer frequency limits for synchronisation (important for FM demodulation).

And for hold range. If the initial input frequency is 50 kHz and the input frequency is increase step by step lower than pull-out range, the PLL will not be locked out until 250kHz.

Yes, but not "step by step"; the input frequency has to be tuned very slowly (if compared with the largest time constant of the loop).

capital_zach

### capital_zach

Points: 2
Thank you for your replies. It is very helpfull.

Hi, perhaps you are interested in a visualization of some simulation results (see pdf attachement).

The diagram contains two cases: Input frequency step after 5msec (a) of 3 kHz and (b) of 6 kHz, see the blue lines.
The response of the PLL is shown in red - and you can see that in case (a) the PLL can follow immediately.
However, in case (b) a pull-in process is necessary.

#### Attachments

• PLL_sync.pdf
140.9 KB · Views: 86

If I'm not mistaken, (a) is lock-in range(lock-in process) right?

If I'm not mistaken, (a) is lock-in range(lock-in process) right?

Not exactly.
The lock-in range applies if the PLL is out of lock and can aquire lock within one beat cycle.
The pull-out range starts from a PLL that has locked (as in case (a)) and can remain in this stage in spite of a frequency step.
But both ranges don't differ very much.

Not exactly.
The lock-in range applies if the PLL is out of lock and can aquire lock within one beat cycle.
The pull-out range starts from a PLL that has locked (as in case (a)) and can remain in this stage in spite of a frequency step.
But both ranges don't differ very much.

Oo I get it now..Thank you for your explanation

Hi Lvw..I have one more question..How can we measure natural frequency wn from the simulation??

Hi Lvw..I have one more question..How can we measure natural frequency wn from the simulation??

The most simple way is in the frequency domain (ac analysis).
The natural frequency is defined for the linear PLL model that has locked.
Thus, you perform an ac simulation for the linear PLL closed-loop model, which has a combined lowpass/bandpass characteristic.
(Comment: In the linear model, the input/output voltages have to be interpreted as phase signals.)
The magnitude starts at 0 dB and exhibits a certain peaking befor it drops. This peak gives you an indication for the pole frequency fp.
The natural frequency can be calculated with the help of the equation:
fn=fp*sqrt(1-D^2) with D=damping coefficient.
D can be approximately derived also from the magnitude plot: D=1/2Qp .
In many cases, D=0.6...07.

Does this help?

Last edited:
capital_zach

### capital_zach

Points: 2
For ac analysis, the input signal should be VAC right?
So far I can understand, how you find fn. But I'm not very clear with Qp. Can you elaborate more about that?

I have expected this question. Qp is the pole quality factor of the second order denominator.
For Qp>0.7071 it is a measure of transfer function peaking. However, in our case it is a bit complicated since the transfer function is a combination of lowpass and bandpass. (For a pure lowpass or bandpass function we have formulas that can be used).
Therefore, Qp cannot be simply derived from the transfer magnitude.
That was the reason for my assumption: D=0.6...0.7 . In this case, there will be a slight peaking of the magnitude response.

capital_zach

### capital_zach

Points: 2
Thank you again for your explanation. You helped me a lot

LvW.. I've one more question. Sorry I asked you a lot. Hope you don't mind.

My question is...how can I measure the center frequency of VCO (simulation)? Is it true that the input voltage of VCO should be zero to find the center frequency of the VCO?

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My question is...how can I measure the center frequency of VCO (simulation)? Is it true that the input voltage of VCO should be zero to find the center frequency of the VCO?

There are many many VCO's from many manufactureres on the market. I think this is a matter of specification (datasheet).

Other than specification, there is no other way to check this?

Other than specification, there is no other way to check this?

When you speak about "measurement" I suppose you have a VCO in hardware on your desk, right?
Don`t you have any documentation? Don't you know the app. frequency range?

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