[SOLVED] High voltage and low voltage MOS design

[rsashwinkumar]

I am intending to design a CMOS current steering DAC to deliver a maximum of 1mA current to drive a load typically of the order of 10kilohms (max). I am using AMIS library for the design. As the output load dictates, i am in need to switch over to a high voltage process. But I decided to keep design with low voltage supply and finally mirror the current onto a High voltage MOS and drive the load. I want to know if the method i suggested above can be used (attachment)? Or please guide me how to do it...**broken link removed****broken link removed**

 

[erikl]

You should be aware that the low-voltage and the high-voltage transistors neither have the same threshold voltages nor the same output conductances, so the current translation won't be one-to-one. You can either adjust the required current transfer ratio by trusting your simulation result, or - if you need better accuracy - you'd have to regulate the high voltage current via a feedback loop with gain (opAmp).

 

[rsashwinkumar]

@erikl : yeah, I would finally size the HV transistor suitably to match the required current... so in that case, can i use this directly?

 

[erikl]

Sure you can do this, but you should also run the corner analyses and check if the accuracy is sufficient for your application.

 

[rsashwinkumar]

thank you!!