high stability LDO with fast transient response

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Hi sir,
i have attached my base paper.Please go through Figure (3). Can you please tell me the approximate Constant Gm Bias Circuit. So that i can attach to my proposed LDO ie.Figure (3). I can design with W and L values,if you give the circuit schematic.
Thanq..
 

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First, pls check the reference voltage DC PSRR. Then check LDO DC PSRR.
What's the DC loop gain @ VIN=2.7V and VIN=4V?

---------- Post added at 10:02 ---------- Previous post was at 09:58 ----------

Constant Gm Bias Circuit is (delta Vgs)/R bias generator circuit.
Pls refer to <<Design of Analog CMOS Integrated Circuits>> by Razavi. Chapter.11, p379
 

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