sar adc transfer function
Maplefie,
Imagine a SAR ADC, where before the comparator there is a switched capacitor which samples the input voltage, and the, successively connects to the reference voltages generated by a resistive ladder, to find the reference voltage nearer the sample input.
Let's take the example of a 12bit SAR ADC with a 2 V full scale range - LSB=2/4096=0.488 mV, which has a resistive ladder that generates the 4095 reference voltages (usually there is some kind of segmentation, but let's consider this simpler case). Finally, consider that the comparator has an offset voltage of 5 mV (i.e. more than 10 LSBs).
Now, let's answer the question: "What is the input voltage voltage value that makes the output code of the SAR ADC change from 0 to 1?"
If there was no offset voltage it would be vi=LSB=0.488mV, but due to the offset it is vi=5.488mV -> more than 10 LSBs away.
No you're saying: "See, told you so...". Well, hold on a bit. And what about the question: "What is the input voltage voltage value that makes the output code of the sar ADC change from 2047 to 2048?". If there was no offset voltage it would be vi=2048xLSB=1V, but due to the offset voltage the transition occurs at vi=1.005 mV -> again more than 10 LSBs away...
So, due to the offset voltage of the comparator, we have a large deviation in both the code transition levels considered above. The point is that, although the deviation is large, IT IS EXACTLY THE SAME FOR THE TWO CODES.... and for ANY other output code that you may consider.
This means that the offset of the comparator shifts the FULL transfer function of the ADC - i.e. causes the ADC to have an offset - but DOES NOT cause nonlinearities (for this to happen the offset of the comparator would have to cause code dependent deviations, which does not happen).
In a SAR ADC, INL and DNL are caused by the mismatches between the elements of the DAC (resistive ladder in the example above)
Regards.
PS1: Silicon proven, no missing codes, decent INL and DNL.
PS2: Thanks Bastos.