There is no plot of CLK_minus, what is it doing?
CLK is not ppropriate as a CML input, you cut off the input
pair hard every time you put it to zero. If CLK_minus does
the same then you may have an interval where both
sides are cut off. You need to ensure the CLK-phase
"handoff" is correct or your "relay race" is ruined.
For realism's sake you ought to be driving the D-pair
and CLK-pair with CML level signals. You may want
to see what those are supposed to be (designs vary,
but output swing looks low and you may need to
change tail/load resistor ratio, ensure that FETs are
sized to be switches and not high value resistors when
"on", etc. A swing of about VT(N) is probably "roughly
right" for a "regular" / "high" VT device choice. A zero-
or low-VT transistor may have trouble getting input
and output levels to coincide neatly (Vds(off) = Vgs(on)).