High speed FPGA , 100 - 400Mhz +

[GhostInABox]

Hi ,

I have some experience designing FPGA IP's for projects( under 100Mhz). My Question is , is there any special design / knowledge that I need to know in-order to design what is considered high speed FPGA designs say 100 - 400Mhz range ? designs. I am talking about designs on an FPGA and not FPGA + board design.

Please let me know if anyone has been involved in so-called high speed FPGA design projects

Thanks in advance

 

[TrickyDicky]

The only thing to consider is good design practice. So plenty of pipelining, minimising logic between registers etc.

You probably also want to consider what really needs to run and that speed and what doesnt - either using a slower clock domain where appropriate or clock enables with plenty of multi-cycle paths specified.

For 400 MHZ, especially when the chip is getting quite full (like 50% + ) be prepared to start putting constraint regions to try and group related logic together.

In summary:
1. Use good design practice
2. Plenty of pipelining
3. Minimise logic in fastest domain
4. Get familiar with SDC and placing regions.
5. Good luck.

 

[sharath666]

I don't think FPGA designs are intended to work at high frequencies considering the use FPGAs are put to nowadays(validation and verification). But to answer your question, I can think of better RTL coding techniques and advanced synthesis options..

 

[TrickyDicky]

I don't think FPGA designs are intended to work at high frequencies considering the use FPGAs are put to nowadays(validation and verification). But to answer your question, I can think of better RTL coding techniques and advanced synthesis options..

There is nothing wrong with 400 MHZ in an FPGA - I have worked on designs where 75% of the FPGA was clocked at 368Mhz. It was painful to try and get it to fit and meet timing - but it was possible. And that was with stratix IV. Stratix V should be a little easier and might be able to be clocked faster.