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High Speed Designs :: Challenges

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englishdogg

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What exactly are the challenges that one faces when you go from say 65nm to 32nm and also in terns frequency where we use gigahertz scles
During synthesis or during place and optimization
 

sakthikumaran87

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less dynamic power but more static power. increased speed and reduced area. but more issues on other parameters like parasitics.
 
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englishdogg

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Thank you for noting the challenegs - pls also help understand how do we take care or control these challenges
i also understand that slew increases at lower nodes.. pls help understand how exactly and the measures taken to control
 

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