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High speed ADC Apeture time

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oven

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In High Speed ADC , S/H is a very important Part for AD.
S/H 's apeture time affect ADC analog signal.
apeture time is relation with ADC CLK??? who know?

for example: apeture time is 1ns,
Different's ADC CLK Frequency can change apeture time???
 

flatulent

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apature jittier

The sample and hold apature jitter is controlled by uncertainties in currents and such. It is mostly not affected by how frequently the sampling takes place.
 

tucura

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Aperture time refers to how long a time the sampling capacitor is exposed to the
input signal. The actual voltage stored in the capacitor depends on the input voltage
at the sampling instant (ideal) and on its derivativatives (cause of errors). The shorter
the aperture time, the less the sampled voltage will depend on the signal derivatives
making it more accurate. Shorter aperture times are much more difficult to achieve.
Higher frequency parts ussually have shorter aperture times, even is used at a lower
operating frequency.

Aperture time is not related to jitter, which is a random variation of the sampling instant.
 

flatulent

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misread

I misread your question. As stated above the time is the duration that the sample and hold is in the track mode. The sampled voltage is held on a capacitor which is connected to the input signal through a semiconductor switch which has some resistance which is nonlinear. The voltage on the capacitor is always behind in time relative to the input signal. If the switch resistance was linear this would always be the same time delay. Since the resistance is at least slightly nonlinear, the time dealy depends upon the difference in old and new voltage. This produces a jitter in time delay which phase modulates the signal.
 

oven

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Thank you for reply my question!

I plan to useing TI's TLC5540 High ADC 40Msps for equivalent time sampling. So,
I very care about S/Hold Time and Aerpture time.

In my design, I have to measure two RF signal's Phase degree. for example, That's a 10Mhz signal, I use a 10.01Mhz Clk for ADC, ADC sampling about 100 periods, equivalent time sampling for 10Mhz signal 1Gs/rate in 1 periods.
Now, we get a serial datas for two analog RF signal, then we can process it in DSP for phase detecting.

In TLC5540's data manual, tds(sampling delay) is 4 ns, taj(aperture jitter time) is 30ps. 10Mhz signal 100 sampling in one periods, it equialent 1Gps ADC rate.
becase TLC5540 aperture jitter time 30ps is nice for 1Gps ADC rate in equivalent sampling.

So , I think, In equivalent sampling application, taj time is a limiter for Maximum equivalent sampling rate,
TLC5540 taj jitter time 30 ps, it's support 30Gps 's maximum sampling rate.
tds(sample/Hold) time is a limiter for Maximum input analog signal frequency,
TLC5540 tds time is 4ns , it's support
1/4*1/2=125Mhz analog signal bandwidth.

Above information, is my opinion for high speed ADC useing in equivalent time
sampling.

Maybe it's have some wrong, please give me some advice.
 

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Other simpler ways

There are several simpler ways to compare the phase of two signals. The first is to use a phase detector circuit. Hittite IC company has one that works up to 1 GHz or so.

If you still want to use the DSP method, you can also hetrodyne both signals down in frequency with the same local oscillator. Their phase relationships will remain the same. The sampling errors are then a smaller fraction of a period and produce less error. You are doing this now with your sampling, but it is much easier with ordinary RF mixers.

You can also reduce the measurement error by averaging over a long time period. This will greatly reduce the random errors and leave the systematic errors.

Let me know if these alternate methods meet your need before I do the math to double check your first ideas.
 

oven

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1) First time, we planned to use a analog mixer for phase detect.
but the different of two signal amplitude affect the output value.
mixer phase=sin(wt+a)*sin(wt) then filter=> phase=sin(a)
if mixer phase=g1*sin(wt+a)*g2*sin(wt) filter=> phase=g1*g2*sin(a);
So if you compare the phase of two signal, at first you have to measure
signal's amplitude , or useing a log amplifier to make a stable amplitude
it eliminate gain affection by phase detecter. like as Analog device inc's AD8302 phase function.

2) the other method, we selected a I/Q detecter for phase measure.
RF 1-30Mhz downconvert 10Khz IF signal, like as Radio receiver, I/Q detecter
IF signal. I/Q detecter need a local sin(wt)/cos(wt).
first channel IF signal g(sin(wt+a))
I/Q Detecter i=g(sin(wt+a)*sin(wt) filter=>i1=g*sin(a)
q=g(sin(wt+a)*cos(wt) filter=>q1=g*cos(a)
=>a=arctan(i1/q1)

second channel IF signal g(sin(wt+b))
I/Q Detecter i=g(sin(wt+b)*sin(wt) filter=>i2=g*sin(b)
q=g(sin(wt+b)*cos(wt) filter=>q2=g*cos(b)
=>b=arctan(i2/q2)

two channel phase measure = a-b = arctan(i1/q1)-arctan(i2/q2);

I/Q detecter isnot need a stable amplitude. Of course, you also can ADC IF signal
and DSP I/Q process.

But all of above method, several mixer are used in system. Mixer have many issues,
In RF 1--30Mhz bandwidth, Mixer have different gain, you have to calibrate the mixer's
error.

if ADC IF siganl for I/Q detecter, why don't we use a high ADC convert for RF, like as
software radio technology, directly ADC RF signal(1Mhz--30Mhz) with equivalent sampling.
The Method of RF ADC convert, DSP process ,this method eliminate the most error in traditional method.

that's my opinion, sorry for my poor english, hope your could undstand my explanation.
my project is design a vecter network analyzer in RF.

my private email: ovenqin@263.net
welcome to detail discussion.
 

flatulent

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better way

Here is my suggestion on how to do it.

1. Use two real track and hold circuits. Clock them from the same source.

2. Use one ADC that is multiplexed between the two track and holds.

3. Keep separate track of the data between the two inputs.

4. Use DSP to calculate amplitude and phase of each set of data. Use many points to refine the accuracy.

This way you know for sure that the two analog signals are sampled identically and that any ADC errors are put to both signals. This way when you take their ratio the errors will be almost eliminated.
 

oven

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useing the same measure channel to eliminate ADC's system error, it's nice ideas. But system have to switch two
signal for one measure ADC, it take many times.
My project request about get data and
process it in 1million second.
Dual ADC is good select for speed reason.
i plan to make a math model for testing
unbalance condition with Dual ADC.

Now I have multisim2001, Matlab6.0.
but I don't know how to begin in Matlab6.0 for ADC system analysis method.
 

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