Hierarchy signal call in VHDL

[imbichie]

Hi All,

Is there any way to call my DUT's signals in the TestBench.
For example in my DUT i have a signal read_en, which is not a port in the DUT.
But in the top tb i need that signal, so is there any hierarchical call for bring that signal in the tb.

Here my testbench name is mem_tb and the DUT name is mem, then how i can call the read_en signal in the testbench

 

[std_match]

It can normally be done, but it's not part of the VHDL standard, so you must check the documentation for your simulator.
I try to avoid this.

If the DUT is not the top level of the design, the simplest solution is to add out ports for the test signals. When you instantiate the block for synthesis, you just leave the test ports unconnected.

That approach is not so good for the top level, since the test signals will be routed to pins when you do synthesis.

Another solution is to use a package inside the DUT to declare the signals you want to monitor.
I have not done it myself, but look at this discussion:

https://groups.google.com/forum/?hl=en&fromgroups=#!topic/comp.lang.verilog/X69Whrp94eE

 

[TrickyDicky]

It can normally be done, but it's not part of the VHDL standard, so you must check the documentation for your simulator.
I try to avoid this.

It is now part of the VHDL 2008 standard. previously you could do it with signal spy or use global signals.

to access an internal signal, you need to find it with the following syntax:

<< signal .TB.DUT.signal_name : std_logic >>

The << >> shows that it is a hierarchical reference. Special characters are @ for the top of the hierarchy and ^ to go up a level.

the best way to handle this is with an alias in the testbench so you dont have to put this syntax every time you read the signal:

alias buried_signal : std_logic is << signal .TB.DUT.signal_name : std_logic >>;

You can also access variables using this method.

I have used it successfully in modelsim (but you'll need modelsim 10+)
See here for reference: