Apr 5, 2008 #1 V venkatesankalidass Junior Member level 3 Joined Jun 14, 2007 Messages 30 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Activity points 1,469 dear all , now currently work with ACTEL FPGA for i am using ACTEL IDE tool in this design i have one problem while i simulate and synthesis ERROR: Mismatch between the portlist of the corresponding symbol of the please help me i whant to finish the project as soons as possible regards venkatesan.k
dear all , now currently work with ACTEL FPGA for i am using ACTEL IDE tool in this design i have one problem while i simulate and synthesis ERROR: Mismatch between the portlist of the corresponding symbol of the please help me i whant to finish the project as soons as possible regards venkatesan.k
Apr 7, 2008 #2 S saleheen Member level 3 Joined Mar 8, 2008 Messages 59 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,633 I think you would need to create the symbol again.. Then try to simulate again.