Hi,
My 2 cents.
HFN is High Fanout Net , other than clock net say net for example, Reset nets, scan enable , or some high fanout nets.
We set the set_max_fanout <some number> during synthesis, what this means we tell to the synthesis tool that more than the max_fanout number treat it as High fanout net , so the tool knows and buffers the nets.
This is what happens during Synthesis stage.
Now the question comes, why do we do this ?
Otherwise the high fanout net will see lot of load and if you try to print the timing report through this net with cap switch enabled you could visualize huge capacitance value and there by huge delays for the cells.
Now you know what is HFN nets and How to treat HFN nets.
Other way of handling these HFN nets is telling or guiding the synthesis tool by saying a command called as "set_ideal_net <scan_enable>". this way the synthesis tool knows the specified net as a high fanout net and does not buffer them .
Now let us come to Clock Tree Synthesis.
CTS[Clock tree synthesis] is also similar to High fanout nets as we know the fanout of the clocks is also high!!!
We can also just buffer them up as we do it for other HFN nets but as this is a clock net considered as a special net , we need to give importance as it has an impact to the complete chip timing. So there is additional constraints in CTS like meeting latency targets, Skew targets and things like that.
There are couple of algorithms used to achieve these targets
* H-TREE
* Balanced H-TREE
* Fish-bone
These were some of the algo's the CTS tools use to ensure that the built Tree for clocks has minimum latency, best possible skew targets , best location of clock-gating cells to ensure reduced power and things like that.
Hope things are clear.
Praise the Lord.
Best Regards,
vlsichipdesigner
https://www.vlsichipdesign.com