Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

HFN synthesis and CTS

Not open for further replies.


Member level 5
Aug 23, 2007
Reaction score
Trophy points
Activity points
hfn synthesis


What is difference B/W HFN synthesis and CTS?

what is hfn synthesis

hfns is high fanout net synthesis usually v will do for high fan out nets like reset and scan

max_fanout max_cap

You mean to say HFNS is for reset and Scan.
and CTS is for clock.I think Clock also comes under Hign FanOut Net(HFN).

Please clear me i am confused.


HFN synthesis is done for the reset pins etc.., before the CTS. This is done during the Zero rc stage while the clock nets are synthesized only during CTS. Because the clock nets are to be laid with extra care.

HFNs are synthesized in front end also.... but at that moment no placement info of standard cells is available... hence backend tool collapses synthesized HFNs. It resenthesizes HFNs based on placement info and appropriately inserts buffer. Target of this synthesis is to meet delay requirements i.e. setup and hold.

For clock no synthesis is carried out in front end... in backend clock tree synthesis tries to meet "skew" targets... There is no skew info for any HFNs

rgds murali
how does Front end engg help BACK end engg in CTS?
can u explain major roles of FE in CTS

HFN synthesis is performed on reset/scan enable/test enable, etc... The requirement is usually max_tran , max_cap, and max_fanout. CTS is for the clocks where you specify the clock tree slew and skew as the requirements, and depending on the tool, you also specify insertion delay.

Any net driving more pins falls under HFNS (High Fanout Net Synthesis).
Even Clock nets fall under this category.

The threshold is determined by the library of buffers you use in the design.
For example in Magma you can use Threshold value to buffer the net which
drives more than this value.

Usually HFNS is done earlier than Clock network building and Clock nets has to be
excluded from getting buffered.
Since Clock network cannot use normal buffers (having no equal transitions).

Hope this helps!!!!!!!

HFN fix the transition problem
CTS fix the latency and clock transition problem


My 2 cents.

HFN is High Fanout Net , other than clock net say net for example, Reset nets, scan enable , or some high fanout nets.
We set the set_max_fanout <some number> during synthesis, what this means we tell to the synthesis tool that more than the max_fanout number treat it as High fanout net , so the tool knows and buffers the nets.
This is what happens during Synthesis stage.

Now the question comes, why do we do this ?
Otherwise the high fanout net will see lot of load and if you try to print the timing report through this net with cap switch enabled you could visualize huge capacitance value and there by huge delays for the cells.

Now you know what is HFN nets and How to treat HFN nets.
Other way of handling these HFN nets is telling or guiding the synthesis tool by saying a command called as "set_ideal_net <scan_enable>". this way the synthesis tool knows the specified net as a high fanout net and does not buffer them .

Now let us come to Clock Tree Synthesis.
CTS[Clock tree synthesis] is also similar to High fanout nets as we know the fanout of the clocks is also high!!!
We can also just buffer them up as we do it for other HFN nets but as this is a clock net considered as a special net , we need to give importance as it has an impact to the complete chip timing. So there is additional constraints in CTS like meeting latency targets, Skew targets and things like that.
There are couple of algorithms used to achieve these targets
* Balanced H-TREE
* Fish-bone

These were some of the algo's the CTS tools use to ensure that the built Tree for clocks has minimum latency, best possible skew targets , best location of clock-gating cells to ensure reduced power and things like that.

Hope things are clear.

Praise the Lord.

Best Regards,
tanz for d wonderful explanations guyz. but hw does the tool diffentiate bt clock nets and hfn nets when we mention max_fanout limit alone. anything above the limit are hfn nets. so hw does the tool seperate the nets as hfns and clock nets.

hi praneshcn,

thanks for the appreciation.

We would define rather create clocks using "create_clock or create_generated_clocks" command correct [Based on Synopsys SDC format].

Then the tool propagates the clock attribute over the complete network.

I believe in your constraints file you also tell the tool so our friend tool knows that he should not disturb the network.
set_dont_touch_network [clock-name]

Hope this answers.

Praise the Lord.

Best regards,

Not open for further replies.

Part and Inventory Search

Welcome to