Help with test bench for this vhdl fsm

[gentleoyink]

Hello, I would like to learn how to write a testbench for a FSM.

Please can you help me write a suitable test bench for the code below. (Please I developed this code to be as simple as it can. However the knowledge gotten from learning it would be applied to a more bigger situation/code).

sorry, here are the codes

--
-----------------------------------
-AND SECTION -
-----------------------------------

-- Subsection AND Gate

library ieee;
use ieee.std_logic_1164.all;



entity andgate is

port (g, h, bit : in STD_LOGIC;

z : out STD_LOGIC);
end andgate;





architecture behavioural of andgate is

Begin
process (bit)

begin

if bit = '0' then

z <= g and h;
else
null;
end if;

end process;

end behavioural;



-----------------------------------
-OR SECTION -
-----------------------------------

-- Subsection OR Gate

--

-- VHDL libraries for standard logic
library ieee;
use ieee.std_logic_1164.all;



entity orgate is

port (x, y, bit : in STD_LOGIC;

d : out STD_LOGIC);
end orgate;


architecture behavioural of orgate is

Begin
process (bit)

begin

if bit = '1' then
d <= x or y;
else
null;
end if;

end process;

end behavioural;



-----------------------------------
-CONTROLLER SECTION -
-----------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity controls is
generic(n : integer := 4);
port
(adds, addin, clock, reset: in STD_LOGIC;
ans : out STD_LOGIC);
end controls;


architecture behavioural of controls is

component andgate
port (g, h, bit : in STD_LOGIC;
z : out STD_LOGIC);
end component;


component orgate
port (x, y, bit : in STD_LOGIC;
d : out STD_LOGIC);
end component;


type states is (none, a, b); --Defines the type of states in the state machine
signal state, next_state : states;
signal added, func: STD_LOGIC;

begin

fsm: process (state)
begin

case state is

when none =>
next_state <= a;

when a =>
next_state <= b;

when b =>
next_state <= a;

end case;

end process fsm;

fsm1: process (clock)

begin
if (reset = '1') then

ans <= '0';

else

if (clock'event) and (clock = '1') then
case state is
when none =>
ans <= '0';

when a =>
added <= '1'; func <= '1';

when b =>
added <= addin; func <= '0';
end case;
end if;
end if;

end process fsm1;


m1 : andgate port map (adds, added, func, ans);

m2 : orgate port map (adds, added, func, ans);

end behavioural;


Thank you for your assistance.

 

[madalin1990]

Well the design of simple testbenches is pretty much the same.You have the blackbox in your case the FSM(which has inputs and outputs).Using the state transition diagram(which you should have it drawn somewhere) you can start modeling the inputs to make your FSM pass through all possible states.Then ,when simulating, you should analyse each state to see if the desired outputs are obtained.

 

[naught]

you can use the XST tool to help you write testbench, new source -> testbench vhdl
the tool sets the basic structure for your design, then you could modify it to your specific needs.