[SOLVED] help with swapping code in verilog

[xpratx]

hi i am trying this swap code
i define "word" as it will be input and output both but now i cannot define it as "reg" and also there comes an error in swap instruction.
is there any way around it??

i know trying input and output for "word" didn't help.

module swap(clock,word);
input clock;
inout [15:0] word;

reg [15:0] word;

always @(posedge clock)
begin
word[15:8] <= word[7:0];
word[7:0] <= word[15:8];
end
endmodule

 

[phoenixpavan]

Hi xpratx,

this thread will solve your problem

https://www.edaboard.com/threads/100303/

cheers

 

[lostinxlation]

Blindly writing the RTL doesn't get you anywhere. Imagine the resulting circuit before coding.

 

[FvM]

At a time, inout can be either in- or output. How about using dedicated in- and outputs outword[ ] <= inword[ ]?

 

[xpratx]

thanks guys for the reply but the problem is i have to swap this way only but i am not able to figure out how to declare "word".

maybe something to do with tristate but i am not sure what to do??

@lostinxlation
ya i didn't think of the circuit i was just trying to run the code here
https://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf
page 3/4