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Help with source synchronous constraints

Tetik

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I have a chip connected to my FPGA which provide the clock with the bidirectionnal data bus. The clock frequency is 100MHz. Here's a view of my implementation for the dataout from the FPGA to the chip.

1593808324256.png

The clock of U0 is connected directly to an IBUF and BUF. After my implementation, I have a timing error. The source clock path (pin->ibuf->bufg->C) is about 5.140ns and my datapath (FDCE->OBUFT->pin) is about 7.0ns. The total delay is higher than the allowed 10ns.

What are my options here?
Do I have to use a MMCM to eliminate the source clock path (phase shift)?
Can I just ignore the source clock path and how to specify it in the constraints file?
Any other options?

For the info, the FPGA is the master of the bus and provides the control signal of the interface but the clock comes from the external chip.

Any help please.
 

vGoodtimes

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you have a variety of options. as this is a chip-to-chip interface, there can be some external factors. the FPGA should have iodelay as well as mmcm. depending on the design, maybe bufio/bufr/bufmr. if these are differential IO, there is also ibufds_diffout which allows real-time analysis of the data window. That said, some of these may add delay. this might be ok if the external IC has some latency options.
 

Tetik

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Thanks for your feedback vGoodtimes.

I have realized that I can't use a MMCM because the clock from the chip is not continuous. Also, my FPGA doesn't have ODELAY primitives. So it lets me little option as to use IDELAY for the inputs and the clock or to invert the clock for the ouput FFs. Not sure if inverting the clock for the output FFs is a good idea or not.

Will try these solutions to see if they might work.

Thanks for your support.
 

vGoodtimes

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interesting. I wasn't aware there was a xilinx fpga with an mmcm that didn't have iodelay.
 

Tetik

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interesting. I wasn't aware there was a xilinx fpga with an mmcm that didn't have iodelay.
Unless I'm wrong , the Spartan 7 has Idelay but no Odelay (HP I/O Only).
 

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