your question is not clear ............anyways you want to basically develop a testbench and drive your module at every posedge so you basically has a DUT(design module) then create a interface for connecting your TB to your DUT and then make generator class or module in your testbench and then drive your DUT signals(i.e. provide stimulus from TB through interface) at posedge and then use system tasks to write it in whatever file you want to write...........refer basic TB creation from @www.TestBench.in