Help with $readmemb in SystemVerilog

[sureshrawal]

Hello,
I have three variables, x,y,z which acts as an input to my SV model. Each of the input are of 16bit length binary data and I have 500 values of them. I need to supply them as input to my module at every posedge of the clock and each after #20ns delay. This is via the TB and also I need to write the output values into a text file. Can someone help me with code. Here is what I have written.

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logic [15:0] X,Y,Z;
logic clk, vectornum;
 
logic [15:0] testvectors [499:0];
 
or or1(.*);
 
initial begin
clk =0;
forever #5ns clk #~clk;
end
 
initial $readmemb("xyz.txt",testvectors);
 
always@(posedge clk)
begin
#20 {X,Y,Z};
testvectors[vectornum];
vectornum=vectornum+1;
end

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[srish]

your question is not clear ............anyways you want to basically develop a testbench and drive your module at every posedge so you basically has a DUT(design module) then create a interface for connecting your TB to your DUT and then make generator class or module in your testbench and then drive your DUT signals(i.e. provide stimulus from TB through interface) at posedge and then use system tasks to write it in whatever file you want to write...........refer basic TB creation from @www.TestBench.in