a suggestion:from a robust design vision,u should use a synchronous circuit to do the communication between FPGA and DSP.
for ur example,maybe it's better to use follow code:
always @ (posedge clk)
if(rd_valid)
....
and the rd_valid should come from a edge detect circuit which detect
the neg edge of "rd",also it's a synchronous circuit.
There are many ways to convert a asynchronous design to a synchronous design,
but firstly we should keep in deep heart the idea that synchronous design is a better
logic design solution.
Just for referrence!