help with parallel interface?

[digi001]

say i have a DSP talking with an FPGA on the XINT parallel bus.

For a DSP Read Action:

1.) DSP pulls FPGA_CS Low and Loads a specific Address
2.) Then on the next clock it pulls RD Low

How quickly are the conditions during always@ checked? Just once?



Is this the proper way to code this?

always@(negedge RD)
begin
if(address==4'b0001 && FPGA_CS==1'b0)
begin

 

[Chops211]

I am more of a VHDL person so I am not 100% sure but I believe that always@(nededge RD) is the same as falling_edge(RD). This means that the conditions are checked immediately after a negative edge is detected on RD.

Think of RD as a negative edge triggered clock...

Hope this helps

 

[Alexium]

Is this the proper way to code this?

always@(negedge RD)
begin
if(address==4'b0001 && FPGA_CS==1'b0)
begin

I don't think so. This would be considered as asynchronous logic, which is a bad desig practice.
Also, if you need to to perform transactions according to a certain protocol (like the one you describe) - you have to use FSM.

 

[FvM]

I don't think so. This would be considered as asynchronous logic, which is a bad desig practice.
Also, if you need to to perform transactions according to a certain protocol (like the one you describe) - you have to use FSM.

Primarly, it's synchronous logic, using RD as a clock. To work as intended, CS and address have to be stable on the falling edge of RD. Considering a typical databus timing, this can be expected.

What you probably mean with "asynchronous logic" is, that RD may be unrelated to the system clock. So although the always block itself isn't bad coding, the data path between both clock domains may be a problem, and e.g. require a domain crossing FIFO. If you don't need to achieve maximum bus access speed, synchronous processing in the system clock domain is mostly preferred. Finally, there's a certain chance, that the data bus may be synchronized to the system clock. Using a common clock source would be the first prerequisite.

 

[Alexium]

What you probably mean with "asynchronous logic" is, that RD may be unrelated to the system clock.

That is indeed what I meant. Should have expressed myself more clear.

 

[FvM]

That is indeed what I meant.

As said, the timing relation between DSP signals won't involve problems. The problem is the relation to the FPGA clock. Assuming, the read action does nothing but transfer data from FPGA to DSP, consistency of the data is the basic issue. If the data can be expected to change at arbitrary moments, the read data will be uncorrect with a finite probability. A signed data item, changing from 0xffff (-1) to 0x0000 (0) has all bits toggling. If sampled at the wrong time, the result can be any signed number due to logic delay skew.

It would go to far to discuss all possible solutions to guarantee data consistency in this situation. But it's important to be aware of the problem.

 

[digi001]

Ok thanks for the responses. So I believe my overall strategy was in fact asynchronous.

Just like any peripheral on a parallel bus (ADC, DAC, memory) they dont require an additional Clock signal from the DSP but rather act as asyncronous Slaves(high Z) until Address, CS and then RD go Low. I want my FPGA to act as this type of peripheral? Is this wrong? Do i really need a Clock signal and make a FSM?

 

[FvM]

I want my FPGA to act as this type of peripheral? Is this wrong? Do i really need a Clock signal and make a FSM?

Typically, a FPGA will be used for complex signal processing. It's hardly possible without a clock.

 

[digi001]

ok so after some reading this weekend, it looks like the best way to get this accomplished is:

always@(RD or FPGA_CS or address)
begin
if(address==4'b0001 && FPGA_CS==1'b0 && RD==0)
begin

 

[FvM]

it looks like the best way to get this accomplished is

Depends on, what's done in the code. If you're only putting some fixed data on the bus, it's O.K.

 

[yadog]

a suggestion:from a robust design vision,u should use a synchronous circuit to do the communication between FPGA and DSP.

for ur example,maybe it's better to use follow code:
always @ (posedge clk)
if(rd_valid)
....

and the rd_valid should come from a edge detect circuit which detect
the neg edge of "rd",also it's a synchronous circuit.

There are many ways to convert a asynchronous design to a synchronous design,

but firstly we should keep in deep heart the idea that synchronous design is a better

logic design solution.

Just for referrence!