Jeff Taylor-Jackson
Newbie level 1
Hi all,
I am new to the list and at my wits end. I am under pressure to complete a design targeting an old Xilinx xc4020. This is part of an upgrade to a legacy design. I am using a dedicated PC because it is the only one loaded with the software to compile these devices!
I am using OrCad 9.1 and Xilinx ISE 4.2. The synthesys tool is Leonardo. The design is done using VHDL. The problem comes when simulating, and compiling. I get errors similar to
: Error : [Load047] no port 'a_in6' found for entity 'RDBK_MUX2'
( this is one of my readback multiplexers) The error message is displayed when I compile or try to simulate. Strangely any individual block of VHDL, does not do this, only on the complete design.
I think the error is telling me that I do not have busses ( ie a_in like above) connected, but they are all there and defined in the code.
Anyone any ideas from the dim and distant past what this is all about?
Any help greatfully recieved.
Kind Regards
Jeff
I am new to the list and at my wits end. I am under pressure to complete a design targeting an old Xilinx xc4020. This is part of an upgrade to a legacy design. I am using a dedicated PC because it is the only one loaded with the software to compile these devices!
I am using OrCad 9.1 and Xilinx ISE 4.2. The synthesys tool is Leonardo. The design is done using VHDL. The problem comes when simulating, and compiling. I get errors similar to
: Error : [Load047] no port 'a_in6' found for entity 'RDBK_MUX2'
( this is one of my readback multiplexers) The error message is displayed when I compile or try to simulate. Strangely any individual block of VHDL, does not do this, only on the complete design.
I think the error is telling me that I do not have busses ( ie a_in like above) connected, but they are all there and defined in the code.
Anyone any ideas from the dim and distant past what this is all about?
Any help greatfully recieved.
Kind Regards
Jeff