s3034585
Full Member level 4
hi guys
i am trying to simulate data bus using hyperlynx. 16bit bus originates from a mcu (66Mhz) then a buffer, FPGA, FLASH, CLD, Level translators. the buffer is tri state bi-directional. when i load the ibis file for buffer it dosnt show an option to put it as input when the fpga is driving the data bus and mcu is reading the data.
i can do the simulation the other way round when the mcu is driving the bus and writting into FPGA, FLASH, CPLD. does any one know how to configure the buffer as indput and simulate the bus when fpga is driving it.
thanks
tama
i am trying to simulate data bus using hyperlynx. 16bit bus originates from a mcu (66Mhz) then a buffer, FPGA, FLASH, CLD, Level translators. the buffer is tri state bi-directional. when i load the ibis file for buffer it dosnt show an option to put it as input when the fpga is driving the data bus and mcu is reading the data.
i can do the simulation the other way round when the mcu is driving the bus and writting into FPGA, FLASH, CPLD. does any one know how to configure the buffer as indput and simulate the bus when fpga is driving it.
thanks
tama