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Help with high speed rail to rail input stage for opamp design

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Jul 9, 2009
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Oregon, USA
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I am trying to design an op-amp with rail to rail inputs and am finding an issue with the symmetric input stage trick. I am limited to a process with no floating gate and nothing fancy like triple well.

I have tried two approaches, one with a simple dual (symmetric) nmos and pmos differential pair and also with a dual folded cascode approach (see Figure 24.48 from Jake Baker's CMOS IC design book any ed.)

The issue I have is that when I analyze each diff pair or folded cascode diff pair by itself I get a good frequency response with say a BW of X and a crossover frequency (f unity) of Y. When I tie them together to form the symmetric diff pair for rail to rail input I get a bandwidth much less than X and a crossover frequency much less than Y. In the frequency response it looks as if putting the outputs together is causing a new pole at low frequencies to be formed.

When I tie them together I either just tie one to an nmos and the other to a pmos and form a crude AB buffer from that, or use Monticelli biasing (floating current mirror), either way I see the same effect.

I can remove the effect by reducing the gain of one of the input pairs such that one is an order of magnitude above/below the other in terms of low frequency gain.

Could this be a simulation artifact/error?
Could I be doing something very wrong when I tie them together?
Does anyone else know of this phenomenon of a tradeoff between bandwidth and having rail-rail inputs?
Is there a workaround or solution to this issue that can give me my rail-rail input without introducing this low frequency pole?

Any help appreciated.

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