No, the fets are fine. I haven't destroyed one of those yet. It is the MPSA42s that keep burning up. I have increased the 200 Ohm resistors to 30K, and placed another resistor between the charging diodes and the collectors. I have also increased the base resistance to 820 Ohms. They still cook, even at light loads.You mean upper left FET is getting destroyed?
I am going to try this. Although, I have seen a couple of other inverter designs that use the MPSA42 for the high side switching. It is rated for 300V and 500mA.I recommend using MOSFET instead of transistor for high power ratings
I really just pulled the circuit straight from the datasheet. On the scope, the modified square wave looks good. Once a load is applied, the switching continues but the transistors get super hot and eventually die.can u give details of your triggering circuit
This is going to worsen the case. Confirm all resistors and capacitors are according to values in schematic. On lower left FET's gate, if 200 ohm resistor value is higher or capacitor value is higher, this condition will happen. Interchange the left and right output of ic to confirm ic is ok. Change the value of both 6800pF capacitor to 1000pF(102n) and see the result. Gate series resistance is 200 ohm(180 to 220 ohm), base resistance 47-100 ohmI have increased the 200 Ohm resistors to 30K
Originally, I thought it was only one side, apologies.there is something wrong on left side construction
You mean at 150 watts, there is no output. If pin4(current sense) is picking some spike pulses, it can shutdown ic and then take more than a second to restart but again a pulse will retrigger.With a 150W load the DVM doesn't even pick up an AC voltage, and the DC supply to the H-bridge stays at ~155V.
It is only a matter of adjusting resistor network on this pin#4. A small capacitor like 6800pF between cs pin and ground pin#5 will also help.CS: Connect the current sense device to this pin. A voltage threshold of 0.725 V triggers a shutdown sequence.An over-current fault triggers an immediate shutdown. After the fault clears, a total of 64 oscillator cycles are required for an entire soft start sequence to occur. First, the outputs and SYNC are kept OFF for at least 56 oscillator cycles.Next, after one or two SYNC pulses, the soft start progressively increases the output duty ratio over the next five to seven oscillator cycles.
Here the deadtime is the duration that both lower or both upper are on.I thought that they were suppose to be on for the same amount of time and the deadtime was the duration that neither was on.
No, I don't have any snubbers on the fets of the H-bridge.Is there any snubber CAP on your 155VDC close to the fets?
Thanks for the diagrams. Okay, so I'm a little confused. The PWM outputs from the IC, do have the appropriate deadtime. They look like your "correct" diagram. In the second pic the blue line is the upper fet, so this wave is also inverted. Then there is a duration of time in the second pic when both fets are off, and this would also be correct, right?Here the deadtime is the duration that both lower or both upper are on.
No, I don't have any snubbers on the fets of the H-bridge.
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