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Help with free FPGA board development

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Member level 4
Jan 11, 2003
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Hello !

I am working in a project for fun and not money, it will be a free project for everybody. Sharing is the way to go.

Anyways, i am having a hard time designing the schematic for Altera's ACEX and APEX with 208 pin encapsulate, because pin-out is not very clear on specification. Also, i know i need a ROM memory conected to the device, JTAG and a oscilator thats it i think, do you think i need something else ?

Thanks for all !!

P.D.- I write this in order to have some help from you, if you want..can use PM.

First about the pinout: I have recently worked with ACEX chips, and, indeed, the documents are less than perfect. Pinout lists inclusive.

I solved the problem by using the free web downloadable MAX II Plus/Leonardo Spectrum (-I think you might consider also Quartus, it's better, but needs also a better PC with a lot of memory). In Floorplan View and chip view the MAX II+ (and Quartus) shows all usable IO pins, and you can see there what is where. For other pins, which are not available for logic I/O, you should use the pdf document from Altera web site. By putting those together you get a pretty good picture of th chip's physical pinout. Which pins are available for user IO depends on which configuration mode you use. The passive serial mode uses least amount of pins and thus gives most user IO pins.

What else you need depends on what you try to do. One thing you do not mention is power supply and bypass capacitors. These chips need good grounding and many bypass capacitors around the chip for both 2.5V and 3.3V pins.

You can either configure the chip via JTAG port, or you may use either serial or paraller configuration mode. Altera AN-116 is very useful (but not too well organized, so it takes a while digging through). See also Altera's download cable documents if you want a simple solution for configuration from a PC or similar.

I hope this helps you at least a little.

Good luck


Attached is the board in my Advanced Microcontroller course. The FPGA, 1K100, is placed on a carrier board. The design is not very neat but it works for me.

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