hlmwps
Newbie level 1
freqmeter by fpga
entity FreqMeter is
port (reset : in std_logic ;
CE : in std_logic ;
bclk : in std_logic;
gclk : in std_logic;
start : in std_logic;
num : in integer range 10 to 1000;
over : out std_logic ;
databus : out std_logic_vector (47 downto 0)
);
end FreqMeter;
architecture Behavioral of FreqMeter is
signal bz_count : integer ;
signal gc_count : integer range 0 to 1000 ;
signal bz_ena,ena : std_logic;
signal clr : std_logic;
signal tmp_start,tmp_over : std_logic;
signal resetn ,resetd : std_logic;
begin
databus <= conv_std_logic_vector(bz_count,48) ;
process (CE,start) begin
if CE='0' and start='0' then
resetn <= '0' ;
elsif CE='0' and rising_edge(start) then
resetn <= '1' ;
end if;
end process;
process (bclk)
begin
if rising_edge (bclk) then
resetd <= resetn ;
end if;
end process;
clr <= resetn and (not resetd) ;
over <= tmp_over ;
process (reset,clr,start)
begin
if reset='0' or clr = '1' then
tmp_start <= '0' ;
elsif falling_edge(start) then
tmp_start <= '1' ;
end if;
end process;
process (reset,clr,tmp_over,ena,tmp_start)
begin
if reset='0' or clr = '1' or (tmp_over='1' and ena='0') then
bz_ena <= '0' ;
elsif rising_edge(tmp_start) then
bz_ena <= '1' ;
end if;
end process;
bzcounter: process (reset,bclk,clr,bz_ena,ena)
begin
if reset='0' or clr = '1' then
bz_count <= 0 ;
elsif rising_edge (bclk) then
if bz_ena = '1' and ena = '1'then
bz_count <= bz_count+ 1;
end if;
end if;
end process;
gccounter: process (reset,gclk,clr,bz_ena)
begin
if reset='0' or clr = '1'then
gc_count <= 0 ;
tmp_over <= '0' ;
ena <= '0' ;
elsif falling_edge (gclk) then
if bz_ena = '1' then
gc_count <= gc_count+ 1;
if gc_count=num then
ena <= '0';
gc_count <= num-1 ;
tmp_over <= '1' ;
else
ena <= '1';
tmp_over <= '0' ;
end if ;
end if;
end if;
end process;
end Behavioral;
Added after 5 minutes:
Above is a VHDL example about frequency counter!
I simulate it with Modelsim 6.0 ! It can work very well and the function is good!
But when I download it into a Xinlix CPLD XC95144XL,its function doesn't do well!
Please help me to find where is the error!
entity FreqMeter is
port (reset : in std_logic ;
CE : in std_logic ;
bclk : in std_logic;
gclk : in std_logic;
start : in std_logic;
num : in integer range 10 to 1000;
over : out std_logic ;
databus : out std_logic_vector (47 downto 0)
);
end FreqMeter;
architecture Behavioral of FreqMeter is
signal bz_count : integer ;
signal gc_count : integer range 0 to 1000 ;
signal bz_ena,ena : std_logic;
signal clr : std_logic;
signal tmp_start,tmp_over : std_logic;
signal resetn ,resetd : std_logic;
begin
databus <= conv_std_logic_vector(bz_count,48) ;
process (CE,start) begin
if CE='0' and start='0' then
resetn <= '0' ;
elsif CE='0' and rising_edge(start) then
resetn <= '1' ;
end if;
end process;
process (bclk)
begin
if rising_edge (bclk) then
resetd <= resetn ;
end if;
end process;
clr <= resetn and (not resetd) ;
over <= tmp_over ;
process (reset,clr,start)
begin
if reset='0' or clr = '1' then
tmp_start <= '0' ;
elsif falling_edge(start) then
tmp_start <= '1' ;
end if;
end process;
process (reset,clr,tmp_over,ena,tmp_start)
begin
if reset='0' or clr = '1' or (tmp_over='1' and ena='0') then
bz_ena <= '0' ;
elsif rising_edge(tmp_start) then
bz_ena <= '1' ;
end if;
end process;
bzcounter: process (reset,bclk,clr,bz_ena,ena)
begin
if reset='0' or clr = '1' then
bz_count <= 0 ;
elsif rising_edge (bclk) then
if bz_ena = '1' and ena = '1'then
bz_count <= bz_count+ 1;
end if;
end if;
end process;
gccounter: process (reset,gclk,clr,bz_ena)
begin
if reset='0' or clr = '1'then
gc_count <= 0 ;
tmp_over <= '0' ;
ena <= '0' ;
elsif falling_edge (gclk) then
if bz_ena = '1' then
gc_count <= gc_count+ 1;
if gc_count=num then
ena <= '0';
gc_count <= num-1 ;
tmp_over <= '1' ;
else
ena <= '1';
tmp_over <= '0' ;
end if ;
end if;
end if;
end process;
end Behavioral;
Added after 5 minutes:
Above is a VHDL example about frequency counter!
I simulate it with Modelsim 6.0 ! It can work very well and the function is good!
But when I download it into a Xinlix CPLD XC95144XL,its function doesn't do well!
Please help me to find where is the error!