help! Vhdl code of 1 bit memory

[kongruxue]

Hi, I am trying to write the code of 1bit SRAM , it has just read /write status. Give two signals we (write) and select_en (this memory cell is choose to work), then the date would be wrote in the memory and stored in Q,and date_out =data_in , otherwise is always in read status ,that means date_out always shows the date which is stored in Q. I was told the 1 bit memory was built by RS-Flip flop, but I don’t know how to combine it . Here is the code, if anyone can help me to check it, or tell me how to use RS-Flip flop to build it ?

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.all;
 
entity SRAM_CELL is
  port(
    CLK         : in std_logic; 
    date_in     : in std_logic;
    we          : in std_logic;   
    select_en   : in std_logic;
    date_out    : out std_logic
  );
end SRAM_CELL ;
 
architecture BEHAVIORAL_SRAM_CELL of SRAM_CELL  is
  signal Q_state : std_logic;
  attribute keep: boolean ;
  attribute keep of Q_state : signal is true;
begin
   process (clk,we)
    begin
     if CLK'event and CLK='1' then
        if select_en CLK='1' then
         if we='1' then
          Q_state <= date_in;
         end if;
        end if;
     end if;
    end process ;
 date_out <= Q_state ;
end BEHAVIORAL_SRAM_CELL;

---

Thank you !

---------- Post added at 14:18 ---------- Previous post was at 13:50 ----------

sorry ,a error, at 23, it should be
if select_en='1' then

 

[shaiko]

In an FPGA you have block RAM and D flip flops. These are different things.
An SR flip flop with an asynchronous reset and synchronous set and reset signals is described like this :

SR_flip_flop : process ( clock , reset ) is
begin
   if reset = '1' then
      Q <= '0' ;
   elsif rising_edge ( clock ) then
      if S = '1' then
         Q <= '1' ;
      elsif R = '1' then
         Q <= '0' ;
      end if ;
   end if ;
end process SR_flip_flop ;

 

[kongruxue]

In an FPGA you have block RAM and D flip flops. These are different things.

Hi, Thanks for the information.Actually I would like to build a 8 bit SRAM up from collection of memory cells(which I was told use RS-FF and I don't kown how) and a Demultiplexer. I already wrote the memory cell code which I post upstairs and a Demultiplexer , I need combine them together. But I not sure how to do it. My thought is :
since there are 5 input :clk,date_in (8 bit),address (8 bit),enable,write(we)
and one output: date_out , through the Demultiplexer to decide which memory cell would be read and wrote.
and now my problem is I don’t know how many memory cell do I need , is 8? And how combine them together also with Demultiplexer. Could you give me some advice?

 

[shaiko]

Again,
FPGA block RAM isn't built with flip flops.
Both circuits are fundamentally different.

Flip flops are higher performance but are also more expensive.
Block RAM is more abundant.

With FPGAs, you can implement a memory array using flip flops - but it shouldn't be called SRAM...

https://www.xilinx.com/support/documentation/user_guides/ug383.pdf