kongruxue
Newbie level 6
Hi, I am trying to write the code of 1bit SRAM , it has just read /write status. Give two signals we (write) and select_en (this memory cell is choose to work), then the date would be wrote in the memory and stored in Q,and date_out =data_in , otherwise is always in read status ,that means date_out always shows the date which is stored in Q. I was told the 1 bit memory was built by RS-Flip flop, but I don’t know how to combine it . Here is the code, if anyone can help me to check it, or tell me how to use RS-Flip flop to build it ?
Thank you !
---------- Post added at 14:18 ---------- Previous post was at 13:50 ----------
sorry ,a error, at 23, it should be
if select_en='1' then
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE ieee.STD_LOGIC_unsigned.all; entity SRAM_CELL is port( CLK : in std_logic; date_in : in std_logic; we : in std_logic; select_en : in std_logic; date_out : out std_logic ); end SRAM_CELL ; architecture BEHAVIORAL_SRAM_CELL of SRAM_CELL is signal Q_state : std_logic; attribute keep: boolean ; attribute keep of Q_state : signal is true; begin process (clk,we) begin if CLK'event and CLK='1' then if select_en CLK='1' then if we='1' then Q_state <= date_in; end if; end if; end if; end process ; date_out <= Q_state ; end BEHAVIORAL_SRAM_CELL;
Thank you !
---------- Post added at 14:18 ---------- Previous post was at 13:50 ----------
sorry ,a error, at 23, it should be
if select_en='1' then
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