use VCS compiler
I need a two dimension array
but VCS can not accept this syntax
EX :
......
....
for(i=0;i<RANGE; i=i+1)
data={chip.mem[127:63],chips.mem[127:63]}
.....
it seems VCS cannot accept a variable i ,
so
Q: How to solve this problem?
it's a simulation model,
two dimension array can let simulate more convinence
it's inside a task :
//===========
reg [32:0]mem[127:0];
reg [127:0]databuf;
task a;
input
output
int i;
begin i=0
@(.....)
repeat(33) begin
databuf={chip.mem[127:63],chips.mem[127:63]} ;
$display("...%h..............".databuf);
.........
end
i=i+1;
...
end
endtask
it's a simulation model,
two dimension array can let simulate more convinence
it's inside a task :
//===========
reg [32:0]mem[127:0];
reg [127:0]databuf;
task a;
input
output
int i;
begin i=0
@(.....)
repeat(33) begin
databuf={chip.mem[127:63],chips.mem[127:63]} ;
$display("...%h..............".databuf);
.........
end
i=i+1;
...
end
endtask
Hi, you define the type databuf as a 128-bit variable(register); however you assign a vector to this scalable varialbe. I think you maybe made a mistake in your coding.
The accessing width of the memory is 128bit or as you defined 32-bit?
For the assignment mechansim, please refer to the extension of verilog2001