generate_debug : if g_enable_debug = true generate
debug_proc_zap : process(i_zap_clk)
begin
if rising_edge(i_zap_clk) then
if zap_active = '1' then
case count is
when 0 => test_ram_inst(0) <= s_i_data & s_q_data;
when 1 => test_ram_inst(1) <= s_i_data & s_q_data;
when 2 => test_ram_inst(2) <= s_i_data & s_q_data;
when 3 => test_ram_inst(3) <= s_i_data & s_q_data;
when 4 => test_ram_inst(4) <= s_i_data & s_q_data;
when 5 => test_ram_inst(5) <= s_i_data & s_q_data;
when 6 => test_ram_inst(6) <= s_i_data & s_q_data;
when 7 => test_ram_inst(7) <= s_i_data & s_q_data;
when others => null;
end case;
count <= count + 1;
else
count <= 0;
end if;
end if;
end process debug_proc_zap;
debug_proc : process(i_clk)
begin
if rising_edge(i_clk) then
if i_debug = X"00000000" then
o_debug <= std_logic_vector(to_signed(sample_count_from_zap,32));
elsif i_debug = X"00000001" then
o_debug <= std_logic_vector(to_signed(sample_count_to_lpddr,32));
elsif i_debug = X"00000002" then
o_debug <= std_logic_vector(to_signed(wr_ack_count,32));
elsif i_debug = X"00000003" then
o_debug <= std_logic_vector(to_signed(data_read_counter,16)) & std_logic_vector(to_signed(samples_read,16));
elsif i_debug = X"00001000" then
o_debug <= test_ram_inst(0);
elsif i_debug = X"00001001" then
o_debug <= test_ram_inst(1);
elsif i_debug = X"00001002" then
o_debug <= test_ram_inst(2);
elsif i_debug = X"00001003" then
o_debug <= test_ram_inst(3);
elsif i_debug = X"00001004" then
o_debug <= test_ram_inst(4);
elsif i_debug = X"00001005" then
o_debug <= test_ram_inst(5);
elsif i_debug = X"00001006" then
o_debug <= test_ram_inst(6);
elsif i_debug = X"00001007" then
o_debug <= test_ram_inst(7);
else
o_debug <= X"DEADDEAD";
end if;
end if;
end process debug_proc;
end generate generate_debug;