help to solve Synchronous BOOST DCDC switching PMOS latch-up problem

[q0w1e2r3]

How to deal with switching P-channel MOSFET in layout ?
For Synchronous BOOST DCDC, when in dead-time, the coil current will be discharged through parasitic P/N junction of large switching PMOS,
and SW node (the connection node of NMOS and coil) voltage with be higher than output voltage, so in tranditional CMOS process,
P+ /Nwell will conduct and parasitic pnp (p+/n-well/p-sub) will be in active region so that it is subject to latch-up, so how to prevent this risk?
If only in transitional CMOS process, how to achieved?

 

[dick_freebird]

You might diode-block the N-well, but that diode has its own
breakdown limits as does the natural Nwell-Psub junction. An
engineered NMOS (bootstrapped) may be a better HSS with
a natural blocking characteristic. If you can get a high voltage
source region, and manage the beyond-rail gate drive. I'm not
too optimistic about vanilla CMOS flows working for you, unless
you're talking 5V or lower product voltage.

Using ESD rules for your PMOS might suppress latchup "well
enough" but you'd still be throwing away all the output current
when SW goes overvoltage, for a big loss term.

I've made flying synchronous boost diodes out of stacked
FETs before, but that was on SOI.

You might elect to just eat the forward losses of a big
Schottky, if those are available at adequate voltage /
leakage in your PDK. Almost any silicided contact system
will produce Schottkies in an N- region, but whether
NWell is light enough doping comes down to cases. And
you still have the NWell-Psub junction limit.