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help to learn SystenVerilog

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nitin_ndg

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I want to learn Systenverilog...
Can any one help me how to start. Or suggest good book.
Is knowledge of verilog or systenC required

Nitin
 

mssajwan

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Hi,
Good to know that so many people are interested in learning SV.
But one suggestion here buddy...but try to search for things as well.
There are so many thread here about SystemVerilog and if u would have
tried u would have got it.
No Hard feelings please.
Now About SV you find some good books here itself in edabaord and there are some wonderful sites to learn as wll.
Google.

But more importantly you can not learn it unless u do hands on....so what i will suggest use SV constructs and make small testbenches...try to understand what each construct do......this is the best way.

cheers
Manmohan
 

    nitin_ndg

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shiv_emf

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system verilog ! well u want to learn for writing design r verification ?
 

vizpal

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I would suggest u have good understanding in C++ and OOP concepts. Some concepts such as classes, class inheritance, virtual classes etc have a great role in System Verilog...
 

sanjay_edaboard

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login to orkut and join system verilog community.
one of the topic threads inlcudes links to lots of system verilog pdfs.

Regards,
Sanjay
 

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