Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] help to answer a RC oscillator question

Status
Not open for further replies.

prcken

Advanced Member level 1
Joined
Nov 1, 2006
Messages
419
Helped
41
Reputation
82
Reaction score
37
Trophy points
1,308
Location
Shanghai
Activity points
4,059
pls look at the images i've uploaded below, can you explain why the amplitude of voltage between the capacitance and resistor finally goes to 2.5V/7.5V
thanks

40_1219452097.jpg

13_1219453019.jpg
 

Initially, c1 is empty, Vc1=0;
V1=0,V2=5,c1 charges;
V1=5,V2=5,c1 discharges;
several periods later. system stable.
Vout is pulse with 2.5-7.5V
 

jianjing526 said:
Initially, c1 is empty, Vc1=0;
V1=0,V2=5,c1 charges;
V1=5,V2=5,c1 discharges;
several periods later. system stable.
Vout is pulse with 2.5-7.5V

actually in the beginning, when V1=0V, Vout is 5V, and Vc1=Vout-V1=5V, think about it~~~~ how it goes to 2.5V in the end?

Added after 2 hours 17 minutes:

i changed R1 to 1M ohm, and re-simulate, the amplitudes are 5V to 10V now
i think it relates to the RC delay time, when R1 is 1k ohm, RC delay time is 20ns, while when R1 is 1M ohm, RC delay time becomes 20µs, while the period of the pulse is 5ns, so........
how to explain clearly

80_1219504745.jpg
 

i changed R1 to 1M ohm, and re-simulate, the amplitudes are 5V to 10V now
i think it relates to the RC delay time, when R1 is 1k ohm, RC delay time is 20ns, while when R1 is 1M ohm, RC delay time becomes 20µs, while the period of the pulse is 5ns, so........
how to explain clearly

Well, sorry for the ambiguous answer.
Let's consider the circuit from the concept "system". It's just a RC network with two inspirations marked as V1 and V2. You get the output from the C1. It's actually a low pass system. It has one pole which located at 1/(2pi*RC). If R1=1K, C1=20p, the pole is about 8MHz. Vin has a constant frequency of 200M and about 1.4dec after the pole. Vin attenuates about 28db with reciprocal phase delay. In this situation, the 2.5V-7.5V pulse is not the final stable state. Maybe much more than 20 pulse can help you!
In the second situation, system pole locates at about 8kHz, for a 200M input. AC magnitude is nearly zero. So the C1 voltage is actually dc 5V which appears at the node out to be a 5V-10V pulse!
 

Well, the system is rather easy to analyze.
Because it is a LINEAR system the rule of superposition may be applied.
Therefore, the steady state condition is as follows:
1.) Without the pulse train the capacitor is charged to 5 volts (output is 5 volts)
2.) Without the dc voltage the circuit related to the output pin is a HIGH pass
which cannot transfer any dc voltage. Thus, at the output there is a pulse train
with an amplitude of 5 volts - centered at 0 volts
(that means: between -2.5 and +2.5 volts)
3.) The sum of both voltages gives a pulse train between (-2.5+5)=+2.5
and (+2.5+5)=7.5 volts.
4.) This applies for all values of R and C - however, the steady state results
after 5...6 time constants (in your case 20 ns or 20 us, respectively).
Regards.

5.) At t=0: Starting with a positive pulse, both voltages (5+5=10 volts) are added and give a maximum of 10 volts.

6.) There is a smooth transition from t=0 towards the steady state at t>5...6 time constants.
 

jianjing526 said:
Well, sorry for the ambiguous answer.
Let's consider the circuit from the concept "system". It's just a RC network with two inspirations marked as V1 and V2. You get the output from the C1. It's actually a low pass system. It has one pole which located at 1/(2pi*RC). If R1=1K, C1=20p, the pole is about 8MHz. Vin has a constant frequency of 200M and about 1.4dec after the pole. Vin attenuates about 28db with reciprocal phase delay. In this situation, the 2.5V-7.5V pulse is not the final stable state. Maybe much more than 20 pulse can help you!
In the second situation, system pole locates at about 8kHz, for a 200M input. AC magnitude is nearly zero. So the C1 voltage is actually dc 5V which appears at the node out to be a 5V-10V pulse!

Two clearer menthods is described.
1. we consider this from the capacitor C1. C1 charges and discharges periodically with different current rate. Charging current is larger compared to discharging current. So charge in C1 is getting more and more, finally to be a stable value.
2. signal processing: we write the transfer function of the system in s-domain. Then input is added. we got a response at the node out. The final response includes two components, steady one and temporary one.
Anyway, the simulation result you got from the output seems meaningless. The voltage across the capacitor C1 is helpful.
Regards!
 

If R is too small, your bandwith is higher to accept some harmonies,
so if you increase R, you can filter the harmonies. COrrect ?
 

LvW said:
............
3.) The sum of both voltages gives a pulse train between (-2.5+5)=+2.5
and (+2.5+5)=7.5 volts.
4.) This applies for all values of R and C - however, the steady state results
after 5...6 time constants (in your case 20 ns or 20 us, respectively).
Regards.

5.) At t=0: Starting with a positive pulse, both voltages (5+5=10 volts) are added and give a maximum of 10 volts.

6.) There is a smooth transition from t=0 towards the steady state at t>5...6 time constants.

thanks all, you are absolurely right.
can you explain in detail about the process of stablizing?

i know the equation of
discharging is V=Vo×exp(-t/RC),
and for charging is V=Vo×{1-exp(-t/RC)},

1/when RC time constant is large, exp(...) is approximately to 1, so it's easy to understand the amplitutdes between 5V to 10V in the large R case.

2/when RC time constant is relatively small, how it dishcarges and charges, finally stablized?

Greetings
Khan
 

Independent on the value of the time constant (that means: for all R,C values) the charge resp. discharge process always follows an e-function.
 

jianjing526 said:
Two clearer menthods is described.
1. we consider this from the capacitor C1. C1 charges and discharges periodically with different current rate. Charging current is larger compared to discharging current. So charge in C1 is getting more and more, finally to be a stable value.
2. signal processing: we write the transfer function of the system in s-domain. Then input is added. we got a response at the node out. The final response includes two components, steady one and temporary one.
Anyway, the simulation result you got from the output seems meaningless. The voltage across the capacitor C1 is helpful.
Regards!

for RC=20ns case, when discharges :exp(-2.5/20)=0.88 ; when charges 1-exp(-2.5/20)=0.12,
1st cycle, 10×0.88≈8.8V, then V1 goes down to 0V, Vout suddenly goes down to 3.5V, and charges to what?....oh, i dont know, i have to go now, talk to u guys later

Added after 2 hours 51 minutes:

LvW said:
。。。。。。。。。。。。。。 always follows an e-function.
what do u mean independent .....and e function, can you kindly give me some statistically deduction? i was stucked at there for a long time, thanks
 

Excuse me, with e-function I mean "exponential" function - as mentioned in your reply from today, 11:58.

discharging is V=Vo×exp(-t/RC),
and for charging is V=Vo×{1-exp(-t/RC)},


These functions, of course, apply for all values for R and C.
 

    prcken

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top