Help! the Problem of "inout"

[mountain]

I have a little problem about the "inout".

The main module is TDSP, the sub module is McBSP0.
"Send_Trig" is used in the McBSP0.
I want use "Send_Trig" as a inout port to trigger the send block and feed back a completion message.

But I can not drive the "Send_Trig" by Test_Send_FLG of TDSP.
In the result of simulation(Modelsim), Test_Send_FLG is green, but the i_Test_Send_FLG is red, and the Send_Trig is red too.

Please help me!

module TDSP(
...
...

)

reg Test_Send_FLG = 0;
wire i_Test_Send_FLG = 0;
...

assign i_Test_Send_FLG = Test_Send_FLG;

McBSP McBSP0(
.RESET (TDSP_nRESET) ,
.CLKI (TDSP_CLKI) ,
.SCLK (TDSP_SCLK) ,
.FSR (TDSP_FSR0) ,
.DR (TDSP_DR0) ,
.FSX (TDSP_FSX1) ,
.DX (TDSP_DX1) ,
.Send_Trig (i_Test_Send_FLG) ,
.RINT (i_TDSP_RINT) ,
.TINT (i_TDSP_TINT) ,
.Data_Out (i_temp_Out) ,
.Data_In (temp_In) ,
.sym_pos (i_sym_pos)
);

endmodule




module McBSP(
RESET ,
CLKI ,
SCLK ,
FSR ,
DR ,
FSX ,
DX ,
Send_Trig ,
RINT ,
TINT ,
Data_Out ,
Data_In ,
sym_pos
);
/************************/
/** 入出力信号の定義 **/
/************************/
input RESET ;
input CLKI ;
input SCLK ;
input FSR ;
input DR ;
input FSX ;
input DX ;
inout Send_Trig ;


reg r_DX = 1'b0;
reg r_FSX = 1'b0;

reg [15: 0] RD1_Data_MEM[15:0];
reg [ 3: 0] RxBit_16_CNT;
reg Send_Trig_Lat = 0;
reg r_Send_TrigO;
reg r_Send_Start;
reg Send_Trig_Drv = 1'b0;
reg r_Tx_Permit = 0;
reg [ 3: 0] TxBit_16_CNT;
reg [15: 0] RCV_Shift_REG;
reg [15: 0] Send_Shift_REG;
reg [ 3: 0] Word_16_CNT;
reg [ 1: 0] r_RINT;
reg [ 1: 0] r_TINT;
reg [15: 0] r_Data_Out ;

reg r_sym_pos ;

assign DX = r_DX;
assign FSX = r_FSX;
assign Data_out= r_Data_Out;
assign sym_pos = r_sym_pos;

bufif1 Send_Trig_C (Send_Trig, r_Send_TrigO, Send_Trig_Drv);

initial
begin
Send_Trig_Drv = 1'b0;
end


/***************************************/
/***** Send Data to Main CMX *****/
/***************************************/
always @ (RESET or posedge SCLK)
begin
if(RESET == 1'h0)
Send_Trig_Lat <= 1'b0;
else
Send_Trig_Lat <= Send_Trig;
end


always @ (RESET or posedge SCLK)
begin
if(RESET == 1'h0)
r_FSX <= 1'b0;
else if(Send_Trig == 1'b1 && Send_Trig_Lat == 1'b0)
r_FSX <= 1'b1;
else
r_FSX <= 1'b0;
end


always @ (RESET or posedge CLKI)
begin
if(RESET == 1'h0)
Send_Trig_Drv <= 1'b0;
else if(r_Tx_Permit == 1'b1)
Send_Trig_Drv <= 1'b1;
else
Send_Trig_Drv <= 1'b0;
end


...

endmodule

 

[nand_gates]

First of all on chip tri stated bus is not allowed unless it is truely needed for ASICs!
Secondly with tri state bus you need to know when exacly to drive the bus! otherwise
you will face bus contension. Know when to drive the bus you need qualifier signal!
In ur case can you beringout Send_Trig_Drv at top level and drive the i_Test_Send_FLG as follows...

wire i_Test_Send_FLG = Send_Trig_Drv ? 'bz : Test_Send_FLG;

Hope this solves ur problem!

 

[mountain]

Thank you for your advice.
Following your suggestion, I checked my code and found i_Test_Send_FLG is initiallized to 1'b1 in the main module.
What you said is true, the tri state bus is difficult to control.

Xie Xie!

 

[blueskystone]

implemention will be :

1. first use two signal in_a and out_a for input and output signals.
2. then USE a inout Pin PAD to connect them .

Hope can answer your Question.