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[Help] stuck-at-0 fault ? redundant fault ?

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shaq

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Dear everyone,

I have 4 quetions about IC testing.

Plz help me!
 

1. to detect stuck-at-0 fault, the test pattern is
a - 0 b - 0 c - 1 d - 1

then 1st and gate op is 0 & 2nd and gate op is 1 or 0(because of stuck-at problem)
& we can observe the 2nd and gate op at output port, as we made 1st and gate op 0.

this pattern can detect the faults
c stuck at 0 & d stuck at 0

some more test patterns for the same stuck-at problem are,
a - 0 b - 1 c - 1 d - 1
a - 1 b - 0 c - 1 d - 1

2. the possible stuck-at faults are,
a - s@0 ( a stuck at zero)
b - s@0
c - s@0
d - s@0
x - s@0 ( let x is output of 1st and gate )
y - s@0 ( let x is output of 1st and gate )
h - s@0

a - s@1 ( a stuck at one)
b - s@1
c - s@1
d - s@1
x - s@1
y - s@1
h - s@1

based on fault equivalance
h s@1 = x s@1 = y s@1
x s@0 = a @0 = b s@0
y s@0 = c @0 = d s@0

so the resultant stuck at faults are
a s@1, b s@1, c s@1, d s@1, h s@1
h s@0, x s@0, y s@0

i think with this you can proceed.
let me know if you have any queries.
 
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