Help required with Xilinx ISE for SPARTAN device

Hi there all,

I would be really glad if saome one could help me out.
We are trying to do a project using the Xilinx ISE 5.2i software.
with the spartan device xcs10-4pc84

Problem 1

when we go to select the device architecture we'll be using the option doesnt give us the menu for Spartan. It only gives for Virtex,VirtexPro,Spartan-II and many others..

We want to work with spartan device xcs10-4pc84 but we can not find a way to do it for no option is given.

PROBLEM 2:

Then as an alternative we decided for ISE 4.1 which supports spartan device as well.. but then it only allows us to go through the EDIF flow.
and not VHDL flow.

We want to start the design using VHDL flow.
but the program just doesnt allow us to implement the VHDL flow no option is shown.

HELP :

It would be really appreciated if someone could help us in this manner
as soon as possible.

Mail me at following address :

200016571@ctech.ac.za
scindian@hotmail.com

Thanking you guys

sanjay

if i remenber ise 5.x don't support spartan, and you can.t use this.
For the second the full version of ise 4.1 work fine whit vhdl.
Do you have webpack ?
If yes the webpack 4.1 is only to fit as say xilinx.
For the ise 4.1 i suggest you to retry to install.
Bye.
G.

I don´t remember if spartan is supported on ISE 5.X, but the second problem is not an installation problem, the reason why you can not use a vhdl flow is that the tool that you have is Alliance 4.X. Alliance package is thought to people working with non Xilinx synthesis tools (Leonardo, Synplify...) so it only support an edif flow.

>Problem 1

Web-ISE series doesn't support "SPARTAN" series.
(Web-ISE 5.X/4.X/3.X)

I recommend use "SPARTAN-2" family.
It is very powerfull & low price.
(Or,Do you need PLCC type ?)

>Problem 2

Oh!?
ISE can design with each VHDL/Verilog/EDIF flow.
Please check your operation of ISE tool.

Alliance package doesn't support VHDL or Verilog flow, please choose Foundation package if you want them.

Yes I have gone through the same problem. What I did was to use Leonardo to Synthesize the design and generate EDIF. I used Xilinx 4.1 to import the EDIF and do place and route.

Hope it helps.