help required in matching transistors with large multiplier

[s3034585]

Hi
I am trying to design layout of 3 transistors, A( m =5), B(m = 5), C(m=30)..
Finding it difficult to match them due to large no of multiplier for one transistor.
Can anyone explain how to match transistors in such situation where the multipliers are not the same.

using interdigitised and common cerntroid one can match in a single row. but this becomes to lengthy and the area is also waisted. Thus thought of using 2-3 rows but due to unequal no of M i am finding it diff.

Can anyone pls let me know about it.
Thanks in Advance
Tama

 

[srivatsan]

Re: help required in matching transistors with large multipl

the first approach to layout is "square circuit config". this can be achieved for every set of transistors or as a whole circuit layout. chekc if you can have it as long single file and then put it in the layout config and see whether the whole circuit looks near "square". this is one approach. also it may be pertinant to have W/L values when you ask such questions....

srivats

 

[Humungus]

Re: help required in matching transistors with large multipl

Implement the following scheme: D = dummy

DDDDDDDD
DCCDCCCD
DCCABCCD
DCBCCACD
DCCABCCD
DCBCCACD
DCCABCCD
DCCCDCCD
DDDDDDDD

This scheme is nearly-common centroid.

 

[sunny153]

Re: help required in matching transistors with large multipl

the above scheme is good. But if you provide the W/L of the transistors, things can be more clear.