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Help required for Design for Testability

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sudarsv

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Hi

This is Sudarshan. I am a Graduate student and I will be doing a project on Design for testability using BIST. I have a few queries regarding the same and It will be really great if I can receive your help. Here are few of my queries:

1. I am completely new to Design for Testability. I have done a few course in VLSI design and have gone thru a couple of papers on Design for Testability concepts. Can you suggest me a good reference text book which I can use to study about DFT.

2. I read in some article that DFT requires different tools. I have access to Cadence in my lab. Is that a sufficient tool for DFT implementation.

3. Can I get some suggestions of academic projects topics for DFT. It will be of great help for me to decide my project work.

Thank you in advance

Regards
Sudarshan
 

sunilbudumuru

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Hello Friend,

Just go through "asic-dft.com" to learn the concepts of DFT.

Regards,
SunilB
 

shakti_pattnaik

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Hi Sudarshan,

1)There's a book called "Design for Test for Digital ICs and Embedded-Core Systems-Alfred Crouch". This is a good book to start with. Or otherwise if you type DFT Basics in google and go to the first link (which is from edaboard) you can very good learning materials.
2)Yes to work on DFT you need some tools from Mentor Graphics (Fastscan, DFT Visualizer, Testkompress). Cadence also has a good tool named SOC Encounter. You can check whether you have a license for this tool but i highly doubt.
3)There are some projects in DFT which has already been done by some people as a thesis work. This you have to search in google.

Thanks and Regards,
Shakti
 

sudarsv

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Hi

Thank you Shakti and Sunil for the response. Well Shakti as you mention that tools like Mentor Graphics are required to perform DFT, I was wondering if we can implement DFT or BIST as a normal circuit design ie adding the extra circuit along with the actual circuit design. Let me know the feasibility of this approach.
 

shaileshdwd

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sudarsv said:
Hi

Thank you Shakti and Sunil for the response. Well Shakti as you mention that tools like Mentor Graphics are required to perform DFT, I was wondering if we can implement DFT or BIST as a normal circuit design ie adding the extra circuit along with the actual circuit design. Let me know the feasibility of this approach.
Hi,
The testing of a design using Bist or ATE is dependent on the design complexity, silicon area utilized and tester cost.
If you are planning for a Logic bist or MBIST for memory testing,
please check the tools availability at your end and then you can go ahead.
Else you can have your own BIST for testing the logic ( if it is a small academic design.
So first choose your design , then design a BIST-RPG( Random pattern generator ) and Comparator. Then start optimizing your BIST according to the need and necessity which helps you.

With BR,
Shail
 

sudarsv

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Hi Shailesh
Thank you for the response.. The explanation in brief is appreciated.

Well I am doing an academic project for my course work. I am planning to design and implement a SRAM with in-built test circuit (MBIST). Do you have any suggestions as to some references, papers, texts for MBIST and their implementation.
 

anssprasad

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Hi Sudarshan
When it comes to projects from the academic point of view I dont think what you do using a tool will add value. What you might be trying to find out is how the tool approaches a particular problem and how it can be improvised. For example take the PODEM algorithm for finding a test vector, how this algorithm can be improved or a new algorithm outperform the existing ones would be a good project in the academic arena. But if you want to do a project that illustrates the DFT flow of an SOC of high complexity, then you can use the tools and demonstrate the flow on an example design.

Thanks
Prasad.
 

pavanhs

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Hi ,
Can u send DFT basics materials


--Pavanhs
 

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