help regarding the mixed design where we have VHDL and Veril

[haneet]

Guyz does any1 know anythng about mixed coding where both VHDL and Verilog is used for designing....

I am supposed to use but don't have any idea..

Haneet

 

[vlsi_whiz]

Re: help regarding the mixed design where we have VHDL and V

In a Mixed design methodology, where you have designs or modules written in
both VHDL and Verilog, the first step you should take is to decide which language
you are going to use for the top-level module.

For example - If you plan to use VHDL for the top-level modules then you can use Verilog for the lower level modules, ie, you can start the design from the bottom-up (design the lowest module and then proceed upwards towards the top).

Verilog can be used for the lowest (leaf) modules and for few other modules of the
next hierarchy levels. You can then use VHDL for the top-level module where you
instantiate the lower level modules. This ofcourse depends on which language you
are good at and are comfortable with. You can also do the reverse... use VHDL for
the lower leaf modules and Verilog for the top-level modules.

You have to be careful about the parameters & Generics used in the design and
also how you are going to instantiate them so that the ports do not get mixed
up.

 

[haneet]

Re: help regarding the mixed design where we have VHDL and V

thnkx dude!!!

I got the clear picture... and im able run the code successfully but i dont understand whtz the use of this kind of design