Help: QAM Modulator - Verilog source code failed to compile

[TTW]

Hi I am an undergraduate student , currently i am doing 1 project
about design a QAM 16 modulator.

I had found a souce code in verilog format about the modulator .

But i failed to compile it in NC simulator ( cadence ) and cant
synthesis it in PKS ( cadence )

Any one can help me or provide me other source code that
can be synthesis in VHDL or verilog format ?

I think that most probably is the source code prob. not my tools' prob.

Thanks a lot .

Below is the source code :

module qam16(in,out);
input [0:3] in;
output out;
voltage in,out;

parameter real freq = 1.0 from (0:inf);
parameter real ampl = 1.0, thresh = 2.5;
parameter real tdelay = 0 from [0:inf),
ttransit = 1/freq;

real x,y,phi;
integer row,col;

analog
begin
row = 2*(V(in[3]) > thresh + V(in[2]) > thresh);
col = 2*(V(in[1]) > thresh + V(in[0]) > thresh);

x = transition(row-1.5,tdelay,ttransit);
y = transition(col-1.5,tdelay,ttransit);

phi = 2 * `M_PI * freq * $realtime();
V(out) <+ ampl * (x * cos(phi) + y * sin(phi));
end
endmodule