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Help!! post-simulation Error!!!

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Wenf.Yeh

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output signals fell to "X" states at post-simulation

there are 6 submodules in my top module

what should I do next to fix the problem?

help me!!
 

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Verify the state of signals connected to this points.
Perhaps, you connected 2 output together.
 

rsrinivas

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master_picengineer said:
Verify the state of signals connected to this points.
Perhaps, you connected 2 output together.
yes...
even though u werent intended to do tat....
check the TB regs if u have initialized them
and it may cause a multiple driver.
this is one common mistake i usually do.....

if this is not the thing check the wire which is connected as an input to the output reg.
if tats X this is not a multiple driver case....
it may be synthesis issue also...

Regards
Srinivas
 

avimit

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Hi,
1. what is post-simulaiton? do you mean post synthesis.
The most common cause of X in netlist(post synth) sims is uninitialized registers in your design.
The second most common cause of X in netlist is a register, which in RTL was reset, wont reset in netlsit.
You need to first see, if all the registers in your design, to which you have applied reset in RTL are actually being reset in netlist.
Due to the way synthesis is done, if you dont use 'set_sync_reset' attribute to your reset signal, then the register which are meant to be reset can go to X in netlist sims.
Kr,
Avi
https://www.vlsiip.com
 

Wenf.Yeh

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thx everyone!!

Hi,Avi!
post-simulation I mean refers to netlist+SDF+testcase-->run
I just replaced the RTL module with corresponding Netlist module one by one today. and find one module has problem.
I will try the ur suggestion
thx!
regards
Arthur
 

rsrinivas

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if u have sdf u shouldn't have a mix of netlist and RTL as netlist has delays(cell and path) and ur RTL doesn't. if u still need to have a mix of both use no timing checks option...
 

    Wenf.Yeh

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wy21century

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Here is some suggestions I can think of
1. check if it is multi-driven net
2. check if the driving flop don't have a reset in start up
3. check if there is timing violations occur if you are doing post-sim with annotated timing information
4. if there is unconnect interface signal
 

    Wenf.Yeh

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Wenf.Yeh

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Thx every one !
I did it!

regards
Arhtur
 

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