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1. what is post-simulaiton? do you mean post synthesis.
The most common cause of X in netlist(post synth) sims is uninitialized registers in your design.
The second most common cause of X in netlist is a register, which in RTL was reset, wont reset in netlsit.
You need to first see, if all the registers in your design, to which you have applied reset in RTL are actually being reset in netlist.
Due to the way synthesis is done, if you dont use 'set_sync_reset' attribute to your reset signal, then the register which are meant to be reset can go to X in netlist sims.
post-simulation I mean refers to netlist+SDF+testcase-->run
I just replaced the RTL module with corresponding Netlist module one by one today. and find one module has problem.
I will try the ur suggestion
Here is some suggestions I can think of
1. check if it is multi-driven net
2. check if the driving flop don't have a reset in start up
3. check if there is timing violations occur if you are doing post-sim with annotated timing information
4. if there is unconnect interface signal