bigworm
Member level 3
Hi,
To generate a bus of signals as the stimulus, I want to build a veriloga model. the input will be a voltage pwl source which in turn gives the voltage vaule versus time with a transition time. the output will be the corresponding bus value. For example, when input voltage is 6, the output will be 1.8V, 1.8V, 0 (that is 3'b110)
my problem is the input signal has transitions(e.g. 0->5 100ps rising) which will be in turn converted to (0,0,1.8V),(0,1.8V,0),(0,1.8V,1.8V),(1.8V,0,0),(1.8V,0,1.8V) by my model, but in fact what I need is 0 and 1.8V,0,1.8V outputs
do you guys know how to realize this model? is there anything like delay so that I can make the transition time invisible to my model?
Thanks!
To generate a bus of signals as the stimulus, I want to build a veriloga model. the input will be a voltage pwl source which in turn gives the voltage vaule versus time with a transition time. the output will be the corresponding bus value. For example, when input voltage is 6, the output will be 1.8V, 1.8V, 0 (that is 3'b110)
my problem is the input signal has transitions(e.g. 0->5 100ps rising) which will be in turn converted to (0,0,1.8V),(0,1.8V,0),(0,1.8V,1.8V),(1.8V,0,0),(1.8V,0,1.8V) by my model, but in fact what I need is 0 and 1.8V,0,1.8V outputs
do you guys know how to realize this model? is there anything like delay so that I can make the transition time invisible to my model?
Thanks!