Another question is that this code generate a single pulse based on a trigger, if it's possible to generate a series of same pulse, like 5 same pulse sequence?
That isn't a question, what exactly is the problem with understanding the code. Or are you expecting a line by line description of everything in the code (sorry not going to happen)? If you don't know the syntax then learn that first with the numerous tutorials on the web.
Another question is that this code generate a single pulse based on a trigger, if it's possible to generate a series of same pulse, like 5 same pulse sequence?
Sure it can be changed, if you know what kind of circuit you want to do this, like if you want a counter to space them out if you want to control it by an FSM or something else entirely. That is where the design comes into engineering.
That isn't a question, what exactly is the problem with understanding the code. Or are you expecting a line by line description of everything in the code (sorry not going to happen)? If you don't know the syntax then learn that first with the numerous tutorials on the web.
Sure it can be changed, if you know what kind of circuit you want to do this, like if you want a counter to space them out if you want to control it by an FSM or something else entirely. That is where the design comes into engineering.
FPGA is the target implementation of your Verilog code/design.
You still haven't clearly mentioned what you want do.
Another question is that this code generate a single pulse based on a trigger, if it's possible to generate a series of same pulse, like 5 same pulse sequence?
Speculating: There is of course clock. If there is an input pulse, then there will be 5 output pulses each of the same pulse-width and equally spaced. Is this the function you want to implement?
FPGA is the target implementation of your Verilog code/design.
You still haven't clearly mentioned what you want do.
Speculating: There is of course clock. If there is an input pulse, then there will be 5 output pulses each of the same pulse-width and equally spaced. Is this the function you want to implement?
There is a trigger as an input pulse, this trigger is from a PC command, using FPGAlink library. The function I am looking for is generating 5 equally spaced output pulses when there is an input pulse received.
I hope you understand that the min pulse width will be equal 1 clock cycle and the min time between two pulses is also equal to 1 clock cycle. You need to enable a counter to start counting up through the input trigger signal. Since you need to generate 5 pulses so let your counter count upto 10. On every even count value (2, 4,6, 8,10) drive a signal high which would be your 5 o/p pulses.
I hope you understand that the min pulse width will be equal 1 clock cycle and the min time between two pulses is also equal to 1 clock cycle. You need to enable a counter to start counting up through the input trigger signal. Since you need to generate 5 pulses so let your counter count upto 10. On every even count value (2, 4,6, 8,10) drive a signal high which would be your 5 o/p pulses.
Thanks a lot dpaul!
I understood the logic that you described and it is helpful. As I am new to verilog, I actually don't know how to implement it. Can you point me some learning materials specific to this topic online? Do you think some modification to this code will be okay or I have to start something completely different?
Another question, is there a easy way to define width for generated pulses?
Online help is there to clear your fundamentals. Customization is your own task. It is pretty simple, do you know how to implement counters?
Step1 - Inside one always block you start incrementing a counter once your input pulse is sensed high by the clock. A 4 bit counter in enough. Simulate and check your design.
Step2 - In another always block just drive a single bit output high on specific values of the count register. Use either if-elseif-else or case statements.
Your work is done!
trig[0] value is unknown, it is not initialized, so it would likely propagate X, don't do such things.
I was able to generate one pulse when the trigger is high based on the code. The code did everything and I only nested it in my module.
The following question I have is how can I repeat this pulse by 5 times?