frs89
Newbie level 5
I NEED SOME HELP TO PUT THIS CODE WORKING. PLEASE!! IF EN='0' then O="0000" else O(x)=y...etc
library IEEE;
use IEEE.std_logic_1164.all;
entity MAIN is
port(
A : in std_logic_vector(0 to 3);
B : in std_logic_vector(0 to 3);
C : in std_logic_vector(0 to 3);
D : in std_logic_vector(0 to 3);
E : in std_logic_vector(0 to 3);
F : in std_logic_vector(0 to 3);
G : in std_logic_vector(0 to 3);
H : in std_logic_vector(0 to 3);
EN : in std_logic;
O : out std_logic_vector(0 to 3)
);
end MAIN;
architecture arch1 of MAIN is
begin
reset: process(EN)
begin
if EN='0' then
O<= "0000";
end if;
end process reset;
O(0) <= '1' when (A=E) or (A=F) or (A=G) or (A=H) else '0';
O(1) <= '1' when (B=E) or (B=F) or (B=G) or (B=H) else '0';
O(2) <= '1' when (C=E) or (D=F) or (E=G) or (F=H) else '0';
O(3) <= '1' when (A=E) or (A=F) or (A=G) or (A=H) else '0';
end arch1;
THE ERROR : Error 554 line 34 : Some bits of signal 'o' are driven more than once
HOW I make a simple if(EN==0){O="0000"} else{O(0)=x , y, etc..} like in Java or C?
Thank you
Flavio Silvestre
library IEEE;
use IEEE.std_logic_1164.all;
entity MAIN is
port(
A : in std_logic_vector(0 to 3);
B : in std_logic_vector(0 to 3);
C : in std_logic_vector(0 to 3);
D : in std_logic_vector(0 to 3);
E : in std_logic_vector(0 to 3);
F : in std_logic_vector(0 to 3);
G : in std_logic_vector(0 to 3);
H : in std_logic_vector(0 to 3);
EN : in std_logic;
O : out std_logic_vector(0 to 3)
);
end MAIN;
architecture arch1 of MAIN is
begin
reset: process(EN)
begin
if EN='0' then
O<= "0000";
end if;
end process reset;
O(0) <= '1' when (A=E) or (A=F) or (A=G) or (A=H) else '0';
O(1) <= '1' when (B=E) or (B=F) or (B=G) or (B=H) else '0';
O(2) <= '1' when (C=E) or (D=F) or (E=G) or (F=H) else '0';
O(3) <= '1' when (A=E) or (A=F) or (A=G) or (A=H) else '0';
end arch1;
THE ERROR : Error 554 line 34 : Some bits of signal 'o' are driven more than once
HOW I make a simple if(EN==0){O="0000"} else{O(0)=x , y, etc..} like in Java or C?
Thank you
Flavio Silvestre