kyjackchan
Junior Member level 3
hi there, i am very new to verilog. I am simply writing a clock generator code
The behavioural simulation seems to be ok with clk_output signal giving a clock, but all i could see from the oscilloscope is a high signal for pin 'clk_output', is there anything i'm missing here?
The behavioural simulation seems to be ok with clk_output signal giving a clock, but all i could see from the oscilloscope is a high signal for pin 'clk_output', is there anything i'm missing here?
Code:
module test(clk_output);
output reg clk_output;
initial
clk_output = 0;
always
#10000000 clk_output = ~clk_output;
endmodule