help on cadence rtl compiler error message

[anwei7208]

cadence rtl compiler

I had a tested verilog code. When I used cadence RTL compiler for synthesis, I have the following error message:

Error : Could not connect positional port. [CDFG-404] [elaborate]
: Cell 'sram_16_256' has no defined positional ordering in file '..........' on line 241
: Error during elaboration

Can anyone explain to me what is "postional"? Thanks very much.

By the way, 'sram_16_256' is a pre-generated register file block.

 

[aravind]

rtl compiler error

Hi Anwei,
This message is related port mapping with different bit size. Could you pls post this question in www.cadence.com logic design forum for more information.