[SOLVED] Help needed with a VHDL code

[YoussefHefny]

hello there, here is my VHDL code :
"library ieee;
use ieee.std_logic_1164.all;

package andpackage is
compackage andpackage is
component and2 is
port (a, b: IN std_logic;
c: OUT std_logic);
end component and2;
end package andpackage;

Use work.andpackage.and2;

entity circuit2 is
port (a, b, x, y: IN std_logic;
d: OUT std_logic);
end entity circuit2;

architecture mixed of ciponent and2 is
port (a, b: IN std_logic;
c: OUT std_logic);
end component and2;
end package andpackage;

Use work.andpackage.and2;

entity circuit2 is
port (a, b, x, y: IN std_logic;
d: OUT std_logic);
end entity circuit2;

architecture mixed of circuit2 is
for gate: and2 use entity work.and2(and2);
signal c,z: std_logic;
begin
gate: and2 port map (a,b,c);
d <= c XOR z;
op: process (x,y) is
begin
z <= x OR y;
end process op;
end architecture mixed;"

the errors are :
"** Error: C:/Modeltech_pe_edu_10.2c/examples/circuit2.vhd(14): (vcom-1136) Unknown identifier "std_logic".

** Error: C:/Modeltech_pe_edu_10.2c/examples/circuit2.vhd(15): (vcom-1136) Unknown identifier "std_logic".

** Error: C:/Modeltech_pe_edu_10.2c/examples/circuit2.vhd(16): VHDL Compiler exiting"

Any help would be greatly appreciated, thanks in advance.

 

[axcdd]

there are so many errors i even dont know where to start....
maybe grab some book about vhdl basic first

library ieee;
use ieee.std_logic_1164.all;

package andpackage is

component and2 is
port (a, b: IN std_logic;
c: OUT std_logic);
end component and2;
end package andpackage;

Use work.andpackage.and2;
library ieee;
use ieee.std_logic_1164.all;
entity circuit2 is
port (a, b, x, y: IN std_logic;
d: OUT std_logic);
end entity circuit2;

architecture mixed of circuit2 is
signal c,z: std_logic;
begin
gate: and2 port map (a,b,c);
d <= c XOR z;
op: process (x,y) is
begin
z <= x OR y;
end process op;
end architecture mixed;

 

[YoussefHefny]

there are so many errors i even dont know where to start....
maybe grab some book about vhdl basic first

Oh i am terribly sorry for this !! i copied multiple codes from different attempts in here. but i did read a bit about VHDL and i 've been doing well with other codes but i seem to have messed up big time with this one.
Thanks a lot for ur help !

 

[K-J]

hello there, here is my VHDL code :
<snip>
"** Error: C:/Modeltech_pe_edu_10.2c/examples/circuit2.vhd(14): (vcom-1136) Unknown identifier "std_logic".

** Error: C:/Modeltech_pe_edu_10.2c/examples/circuit2.vhd(15): (vcom-1136) Unknown identifier "std_logic".

** Error: C:/Modeltech_pe_edu_10.2c/examples/circuit2.vhd(16): VHDL Compiler exiting"

Any help would be greatly appreciated, thanks in advance.

Perhaps you should read my reply to your question in comp.lang.vhdl. But to avoid the suspense, the following lines of code need to be placed both before the package definition (where you have them now) and also prior to the entity definition.

library ieee;
use ieee.std_logic_1164.all;

Kevin Jennings