ghegde
Member level 1
Hello,
I have designed a Clock buffer(Inverter chain buffer).
Here are my pre(schematic ) and post layout simulation data,
Definition:
Static current : Current drawn when input signal is Zero.
Peak current : Peak current drawn when the circuit is active (i.e when signal is applied to input).
Avg. current : Average current drawn when the circuit is active.
Now my question is,
1) Whether these results are expected?
2)There is a huge increase in static current(while other two are reduced). What could be the reason?
I am using AMS 0.35um technology.It is a 6 stage inverter chain.
Thanks
I have designed a Clock buffer(Inverter chain buffer).
Here are my pre(schematic ) and post layout simulation data,
Parameter | Pre | Post |
Static current | 14.79pA | 57.31pA |
Peak current | 7.99mA | 7.03mA |
Avg. current | 0.671mA | 0.628mA |
Definition:
Static current : Current drawn when input signal is Zero.
Peak current : Peak current drawn when the circuit is active (i.e when signal is applied to input).
Avg. current : Average current drawn when the circuit is active.
Now my question is,
1) Whether these results are expected?
2)There is a huge increase in static current(while other two are reduced). What could be the reason?
I am using AMS 0.35um technology.It is a 6 stage inverter chain.
Thanks